Abstract: A method of manufacturing a thin film transistor includes: forming an active pattern on a substrate; forming an insulating layer and a gate electrode layer on the active pattern in order; forming a photoresist pattern on the gate electrode layer; forming a preliminary gate electrode by wet etching the gate electrode layer using the photoresist pattern; forming an insulating pattern by dry etching the insulating layer using the photoresist pattern and the preliminary gate electrode; and forming a gate electrode by wet etching a side surface of the preliminary gate electrode using the photoresist pattern.

Abstract: A display device includes a base layer; a first pattern disposed on the base layer; an insulating layer disposed on the first pattern and including layers; and a second pattern disposed on the insulating layer. At least two of the layers of the insulating layer include a same material.

Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.

Abstract: A display device includes a substrate, a first conductive layer on the substrate, the first conductive layer including a data signal line, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, the semiconductor layer including a first semiconductor pattern, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, the second conductive layer including a gate electrode disposed to overlap the first semiconductor pattern, a transistor first electrode disposed to overlap a part of the first semiconductor pattern, wherein the transistor first electrode is electrically connected to the data signal line through a contact hole that penetrates the first and second insulating layers, and a transistor second electrode disposed to overlap another part of the first semiconductor pattern.