Patents by Inventor Seung-gil Yang
Seung-gil Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967614Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.Type: GrantFiled: April 7, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Gil Yang, Seung Min Song, Soo Jin Jeong, Dong Il Bae, Bong Seok Suh
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Patent number: 11923456Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.Type: GrantFiled: April 18, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
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Patent number: 7759248Abstract: A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device may include a conductive layer doped with impurities, a non-conductive layer on the conductive layer and undoped with impurities, an interlayer insulating film on the non-conductive layer and having a contact hole for exposing an upper surface of the non-conductive layer, an ohmic tungsten film on the contact hole, a lower portion of the ohmic tungsten film permeating the non-conductive layer to come in contact with the conductive layer, a tungsten nitride film on the contact hole on the ohmic tungsten film, and a tungsten film on the tungsten nitride film to fill the contact hole.Type: GrantFiled: October 24, 2006Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Hwee Cheong, Sang-Woo Lee, Jong-Won Hong, Seung-Gil Yang, Kyung-In Choi, Hyun-Bae Lee
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Patent number: 7507627Abstract: In one embodiment, a nonvolatile memory device can be fabricated by forming first metallic dots on a charge storage film using first source gas, forming substitution dots on the charge storage film on which the first metallic dots are formed and forming second metallic dots using a second source gas.Type: GrantFiled: March 14, 2007Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Hwee Cheong, Sang-Woo Lee, Jin-Ho Park, Seung-Gil Yang, Brad H. Lee
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Patent number: 7410892Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.Type: GrantFiled: March 15, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Sook Park, Gil-Heyun Choi, Sang-Bom Kang, Kwang-Jin Moon, Hyun-Su Kim, Seung-Gil Yang
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Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer
Patent number: 7384866Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.Type: GrantFiled: March 31, 2005Date of Patent: June 10, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-young Yun, Gil-heyun Choi, Byung-hee Kim, Jong-myeong Lee, Seung-gil Yang, Jung-hun Seo -
Publication number: 20080003711Abstract: In one embodiment, a nonvolatile memory device can be fabricated by forming first metallic dots on a charge storage film using first source gas, forming substitution dots on the charge storage film on which the first metallic dots are formed and forming second metallic dots using a second source gas.Type: ApplicationFiled: March 14, 2007Publication date: January 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong-Hwee CHEONG, Sang-Woo LEE, Jin-Ho PARK, Seung-Gil YANG, Brad H. LEE
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Patent number: 7285493Abstract: Methods for depositing a metal layer on an integrated circuit device comprising providing a transition metal precursor, carrier gas and hydrogen gas to a deposition chamber such that the partial pressure of the precursor and carrier gas exceeds about 0.25 Torr and the partial pressure of hydrogen gas exceeds about 2.5 Torr are disclosed. Methods of forming a cobalt layer on an integrated circuit device are also disclosed.Type: GrantFiled: April 6, 2004Date of Patent: October 23, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Bom Kang, Gil-Heyun Choi, Kwang-Jin Moon, Hyun-Su Kim, Seung-Gil Yang
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Publication number: 20070134914Abstract: A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device may include a conductive layer doped with impurities, a non-conductive layer on the conductive layer and undoped with impurities, an interlayer insulating film on the non-conductive layer and having a contact hole for exposing an upper surface of the non-conductive layer, an ohmic tungsten film on the contact hole, a lower portion of the ohmic tungsten film permeating the non-conductive layer to come in contact with the conductive layer, a tungsten nitride film on the contact hole on the ohmic tungsten film, and a tungsten film on the tungsten nitride film to fill the contact hole.Type: ApplicationFiled: October 24, 2006Publication date: June 14, 2007Inventors: Seong-Hwee Cheong, Sang-Woo Lee, Jong-Won Hong, Seung-Gil Yang, Kyung-In Choi, Hyun-Bae Lee
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Publication number: 20060194432Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.Type: ApplicationFiled: March 15, 2006Publication date: August 31, 2006Inventors: Hee-Sook Park, Gil-Heyun Choi, Sang-Bom Kang, Kwang-Jin Moon, Hyun-Su Kim, Seung-Gil Yang
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Patent number: 7045842Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.Type: GrantFiled: February 13, 2004Date of Patent: May 16, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Sook Park, Gil-Heyun Choi, Sang-Bom Kang, Kwang-Jin Moon, Hyun-Su Kim, Seung-Gil Yang
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Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer
Patent number: 6955983Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.Type: GrantFiled: February 24, 2003Date of Patent: October 18, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-young Yun, Gil-heyun Choi, Byung-hee Kim, Jong-myeong Lee, Seung-gil Yang, Jung-hun Seo -
Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer
Publication number: 20050179141Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.Type: ApplicationFiled: March 31, 2005Publication date: August 18, 2005Inventors: Ju-young Yun, Gil-heyun Choi, Byung-hee Kim, Jong-myeong Lee, Seung-gil Yang, Jung-hun Seo -
Publication number: 20040203233Abstract: Methods and compositions for depositing a metal layer on a integrated circuit device comprising a transition metal precursor and carrier gas such that a partial pressure of the precursor and carrier gas exceeds about 0.25 Torr are disclosed. Processes for the preparation of depositing a cobalt precursor on an integrated circuit device are also disclosed.Type: ApplicationFiled: April 6, 2004Publication date: October 14, 2004Inventors: Sang-Bom Kang, Gil-Heyun Choi, Kwang-Jin Moon, Hyun-Su Kim, Seung-Gil Yang
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Publication number: 20040178505Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.Type: ApplicationFiled: February 13, 2004Publication date: September 16, 2004Inventors: Hee-Sook Park, Gil-Heyun Choi, Sang-Bom Kang, Kwang-Jin Moon, Hyun-Su Kim, Seung-Gil Yang
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Publication number: 20040082167Abstract: A recess is formed in a microelectronic substrate, and then a metal-containing layer is formed that conforms to an inner surface of the recess and to a surface of the substrate adjacent the recess. A carbon concentration in a portion of the metal-containing layer on the surface of the substrate adjacent the recess is decreased in comparison to a portion of the metal-containing layer within the recess, e.g., using a plasma treatment that has a greater effect on the surface outside of the recess. Aluminum is then deposited on the metal-containing layer to form an aluminum layer that conforms to the inner surface of the recess and to the surface of the substrate adjacent the recess. Preferably, the carbon concentration in the portion of the metal-containing layer within the recess is sufficiently great to cause aluminum to deposited at a greater rate on the portion of the metal-containing layer within the recess.Type: ApplicationFiled: July 16, 2003Publication date: April 29, 2004Inventors: Jung-Hun Seo, Gil-Heyun Choi, Ju-Young Yun, Byung-Hee Kim, Seung-Gil Yang
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Publication number: 20040038517Abstract: A contact structure is formed by forming an interlayer dielectric on a substrate having a semiconductive region. A contact hole is formed in the interlayer dielectric to expose the semiconductive region. A conductive structure is formed adjacent to the contact hole. Spacers are formed on inner sidewalls of the contact hole. A cobalt silicide layer is formed at a bottom of the contact hole. The spacers are configured to electrically isolate the cobalt silicide layer from the conductive structure. A conductive layer is formed on the cobalt silicide layer in the contact hole.Type: ApplicationFiled: June 30, 2003Publication date: February 26, 2004Inventors: Sang-Bum Kang, Kwang-Jin Moon, Seung-Gil Yang, Hee-Sook Park
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Publication number: 20030222346Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.Type: ApplicationFiled: February 24, 2003Publication date: December 4, 2003Inventors: Ju-Young Yun, Gil-Heyun Choi, Byung-Hee Kim, Jong-Myeong Lee, Seung-Gil Yang, Jung-Hun Seo