Abstract: A circuit for sensing and amplifying a signal of a signal line includes a sensing voltage generation circuit including a sensing circuit, the sensing voltage generation circuit configured to generate a sensing voltage by sensing and amplifying a line input signal based on a bias voltage, and a bias voltage generation circuit including a replication circuit, the replication circuit having a structure identical to a structure of the sensing circuit and generating a replication voltage and the bias voltage generation circuit configured to generate the bias voltage by comparing the replication voltage with a logic threshold level.

Abstract: A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.

Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.

Abstract: A memory may include: a bit line sense amplifier circuit configured to operate based on voltages supplied to a pull-up voltage terminal and a pull-down voltage terminal, provide an offset between a first bit line and a second bit line during an offset canceling period, and amplify a voltage difference between the first bit line and the second bit line during an amplification period; a first down-converter configured to generate a second pull-up voltage by down-converting a first pull-up voltage and supply the generated second pull-up voltage to a first node; a capacitor electrically connected to the first node; a charging component configured to charge the capacitor with the first pull-up voltage before the offset canceling period; and a first pull-up supply configured to supply a voltage of the first node to the pull-up voltage terminal during the offset canceling period.

Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.

Abstract: A memory may include: a bit line sense amplifier circuit configured to operate based on voltages supplied to a pull-up voltage terminal and a pull-down voltage terminal, provide an offset between a first bit line and a second bit line during an offset canceling period, and amplify a voltage difference between the first bit line and the second bit line during an amplification period; a first down-converter configured to generate a second pull-up voltage by down-converting a first pull-up voltage and supply the generated second pull-up voltage to a first node; a capacitor electrically connected to the first node; a charging component configured to charge the capacitor with the first pull-up voltage before the offset canceling period; and a first pull-up supply configured to supply a voltage of the first node to the pull-up voltage terminal during the offset canceling period.

Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.

Abstract: A sense amplifier includes a latch type sense unit that detects a voltage difference between a bit line and a bit line bar and causes a voltage difference between a first latch output node and a second latch output node. The sense amplifier further includes a first latch connection unit that electrically connects the bit line to and disconnects the bit line from the first latch output node.

Abstract: A sense amplifier includes a latch type sense unit that detects a voltage difference between a bit line and a bit line bar and causes a voltage difference between a first latch output node and a second latch output node. The sense amplifier further includes a first latch connection unit that electrically connects the bit line to and disconnects the bit line from the first latch output node.

Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.

Abstract: A nonvolatile memory device may include a cell array and a sense amplifier. The cell array may be coupled with a global bit line and a global word line, and is applied with a read voltage through the global bit line. The sense amplifier may generate an output signal based on a voltage level of a sensing node which is coupled with the cell array through the global word line, and control the voltage level of the sensing node.

Abstract: A nonvolatile memory device may include a cell array and a sense amplifier. The cell array may be coupled with a global bit line and a global word line, and is applied with a read voltage through the global bit line. The sense amplifier may generate an output signal based on a voltage level of a sensing node which is coupled with the cell array through the global word line, and control the voltage level of the sensing node.

Abstract: A semiconductor apparatus suitable for operating by being applied with a plurality of external voltages from an exterior includes an initialization block configured to enable an initialization signal until all of the plurality of external voltages are higher than preset voltage levels after the plurality of external voltages are initially applied to the semiconductor apparatus; and an internal circuit configured to perform an initialization operation in response to the initialization signal.