Patents by Inventor Seung Han Ryu

Seung Han Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10782762
    Abstract: An electronic device may include a semiconductor memory device, a central processing device that controls an operation of the semiconductor memory device, and a power supply that supplies power to the semiconductor memory device and the central processing device, and the power supply may include a power controller that receives external power and generates an internal voltage and a charge voltage, an auxiliary power unit that is charged by the charge voltage in a normal mode and provides charged power when sudden power loss occurs, and a charge voltage conversion unit that supplies the auxiliary power unit with the charge voltage at a first level in the normal mode, and converts the first level of the charge voltage to a second level higher than the first level and supplies the charge voltage to the auxiliary power unit in a test mode.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Seung Han Ryu
  • Publication number: 20190339761
    Abstract: An electronic device may include a semiconductor memory device, a central processing device that controls an operation of the semiconductor memory device, and a power supply that supplies power to the semiconductor memory device and the central processing device, and the power supply may include a power controller that receives external power and generates an internal voltage and a charge voltage, an auxiliary power unit that is charged by the charge voltage in a normal mode and provides charged power when sudden power loss occurs, and a charge voltage conversion unit that supplies the auxiliary power unit with the charge voltage at a first level in the normal mode, and converts the first level of the charge voltage to a second level higher than the first level and supplies the charge voltage to the auxiliary power unit in a test mode.
    Type: Application
    Filed: September 26, 2018
    Publication date: November 7, 2019
    Inventor: Seung Han RYU
  • Publication number: 20190139680
    Abstract: Provided are a nanostructure network and a method of fabricating the same. The nanostructure network includes nanostructures having a poly-crystalline structure formed by self-assembly of the nanostructures. The method includes preparing a nanostructure solution in which nanostructures are dispersed in a first solvent, forming a nanostructure ink by adding the nanostructure solution into a second solvent having a viscosity higher than that of the first solvent, coating a surface of a substrate with the nanostructure ink, and forming a nanostructure network by evaporating the first solvent and the second solvent included in the nanostructure ink coated on the substrate.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventors: Yong-Ho CHOA, Young Tae KWON, Seung Han RYU
  • Patent number: 10256396
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: April 9, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan Soo Kim, Dong Joon Kim, Seung Han Ryu, Hee Baeg An, Jong Yeul Jeong, Kyung Soo Kim, Kang Sup Shin
  • Publication number: 20170110643
    Abstract: The present invention relates to a thermoelectric composite in which a thermoplastic polymer constitutes a matrix, and one or more types of electroconductive materials selected from the group consisting of chalcogen materials and chalcogenides are dispersed at grain boundaries between the thermoplastic polymer particles to form a conductive pathway, wherein an average size of the electroconductive materials is smaller than an average size of the thermoplastic polymer particles, the chalcogen materials are one or more substances selected from the group consisting of sulfur (S), selenium (Se), tellurium (Te), and polonium (Po), the chalcogenides are compounds containing one or more chalcogens selected from the group consisting of S, Se, Te, and Po, and the thermoelectric composite has a thermal conductivity of 0.1 to 0.5 W/m·K. The present invention also relates to a method of preparing the thermoelectric composite.
    Type: Application
    Filed: June 4, 2015
    Publication date: April 20, 2017
    Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventors: Yong Ho Choa, Seil Kim, Yo Min Choi, Seung Han Ryu
  • Publication number: 20160322561
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Kwan Soo KIM, Dong Joon KIM, Seung Han RYU, Hee Baeg AN, Jong Yeul JEONG, Kyung Soo KIM, Kang Sup SHIN
  • Patent number: 9419206
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: August 16, 2016
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan Soo Kim, Dong Joon Kim, Seung Han Ryu, Hee Baeg An, Jong Yeul Jeong, Kyung Soo Kim, Kang Sup Shin
  • Patent number: 9018028
    Abstract: A magnetic sensor and a manufacturing method thereof are provided. The magnetic sensor includes: a substrate comprising a plurality of Hall elements, a protective layer formed on the substrate, a base layer formed on the protective layer, and an integrated magnetic concentrator (IMC) formed on the base layer and comprising a surface with an elevated portion. The base layer has a larger cross-sectional area than the IMC.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: April 28, 2015
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Seung Han Ryu, Jong Yeul Jeong, Kwan Soo Kim
  • Publication number: 20140367813
    Abstract: A magnetic sensor and a manufacturing method thereof are provided. The magnetic sensor includes: a substrate comprising a plurality of Hall elements, a protective layer formed on the substrate, a base layer formed on the protective layer, and an integrated magnetic concentrator (IMC) formed on the base layer and comprising a surface with an elevated portion. The base layer has a larger cross-sectional area than the IMC.
    Type: Application
    Filed: August 9, 2013
    Publication date: December 18, 2014
    Applicant: MagnaChip Seminconductor, Ltd.
    Inventors: Seung Han RYU, Jong Yeul JEONG, Kwan Soo KIM
  • Publication number: 20140252514
    Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.
    Type: Application
    Filed: July 25, 2013
    Publication date: September 11, 2014
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan Soo KIM, Dong Joon KIM, Seung Han RYU, Hee Baeg AN, Jong Yeul JEONG, Kyung Soo KIM, Kang Sup SHIN
  • Patent number: 8599593
    Abstract: A memory system includes a memory device configured to read control data for operating conditions from a content addressed memory (CAM) block by performing a CAM read operation and to perform a data input/output operation based on the control data and a memory controller configured to store the control data of the memory device and to determine whether the memory device is to perform the CAM read operation by comparing the stored control data with the control data of the memory device when an operating mode of the memory device or the memory controller changes.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: December 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Han Ryu
  • Publication number: 20120110401
    Abstract: A semiconductor memory apparatus includes: a first data counting unit configured to count respective programming levels of a plurality of input data and output a plurality of first data counting codes having a code value corresponding to the number of respective programming levels; a data read unit configured to sense data stored in a memory block having the plurality of input data programmed therein, based on a voltage level of a plurality of read bias signals, and output the sensed result as a plurality of output data; a second data counting unit configured to count respective programming levels of the plurality of output data and output a plurality of second data counting codes having a code value corresponding to the number of respective programming levels; a read bias control unit configured to compare the plurality of first data counting codes with the plurality of second data counting codes and output a bias control code having a code value corresponding to the comparison result; and a read bias genera
    Type: Application
    Filed: December 31, 2010
    Publication date: May 3, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Seung Han RYU, Beom Ju SHIN, Jung Woo LEE, Myeong Woon JEON
  • Publication number: 20120057389
    Abstract: A memory system includes a memory device configured to read control data for operating conditions from a content addressed memory (CAM) block by performing a CAM read operation and to perform a data input/output operation based on the control data and a memory controller configured to store the control data of the memory device and to determine whether the memory device is to perform the CAM read operation by comparing the stored control data with the control data of the memory device when an operating mode of the memory device or the memory controller changes.
    Type: Application
    Filed: July 12, 2011
    Publication date: March 8, 2012
    Inventor: Seung Han RYU
  • Patent number: 8014207
    Abstract: A nonvolatile memory device includes an encoder configured to perform a scramble operation on input data, a digital sum value (DSV) generator configured to generate a DSV indicating a difference between a number of data ‘0’ and a number of data ‘1’ in the input data encoded by the encoder, a main cell unit of a page of a memory cell array, wherein the main cell unit is configured to store the input data encoded by the encoder, a spare cell unit of the page, wherein the spare cell unit is configured to store the DSV generated by the DSV generator, and a read voltage setting unit configured to determine a read voltage for the page by comparing a DSV generated from the stored data of the main cell unit and the stored DSV of the spare cell unit.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 6, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Han Ryu, Joong Seob Yang, Seung Jae Chung
  • Publication number: 20100182830
    Abstract: A nonvolatile memory device includes an encoder configured to perform a scramble operation on input data, a digital sum value (DSV) generator configured to generate a DSV indicating a difference between a number of data ‘0’ and a number of data ‘1’ in the input data encoded by the encoder, a main cell unit of a page of a memory cell array, wherein the main cell unit is configured to store the input data encoded by the encoder, a spare cell unit of the page, wherein the spare cell unit is configured to store the DSV generated by the DSV generator, and a read voltage setting unit configured to determine a read voltage for the page by comparing a DSV generated from the stored data of the main cell unit and the stored DSV of the spare cell unit.
    Type: Application
    Filed: December 30, 2009
    Publication date: July 22, 2010
    Inventors: Seung Han RYU, Joong Seob Yang, Seung Jae Chung