Abstract: A display device includes a glass substrate including a first surface, a second surface opposite to the first surface, and a side surface between the first and second surfaces, an outermost structure disposed on the first surface and adjacent to an edge of the glass substrate, and a display area including a plurality of emission areas spaced apart from the edge on the first surface of the glass substrate. The side surface has a curved shape with the edge protruding to an outermost side of the glass substrate, the side surface includes a first side surface between the edge and the first surface, and a second side surface between the edge and the second surface and having a different curvature from the first side surface, and the glass substrate includes an edge area on the first surface, adjacent to the edge, and, in which processing traces are left.

Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.

Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.

Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.

Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.

Abstract: Provided is a manufacturing method of a semiconductor device including providing a substrate including a first region and a second region, forming active fins in the first region and the second region, forming gate electrodes which intersect the active fins and have surfaces facing side surfaces of the active fins, forming an off-set zero (OZ) insulation layer covering the active fins, forming a first residual etch stop layer and a first hard mask pattern which cover the first region, injecting first impurities into the active fins of the second region, removing the first hard mask pattern and the first residual etch stop layer, forming second residual etch stop layer and a second hard mask pattern which cover the second region, injecting a second impurities into the active fins of the first region, and removing the second residual etch stop layer and the second hard mask pattern.

Abstract: Provided is a manufacturing method of a semiconductor device including providing a substrate including a first region and a second region, forming active fins in the first region and the second region, forming gate electrodes which intersect the active fins and have surfaces facing side surfaces of the active fins, forming an off-set zero (OZ) insulation layer covering the active fins, forming a first residual etch stop layer and a first hard mask pattern which cover the first region, injecting first impurities into the active fins of the second region, removing the first hard mask pattern and the first residual etch stop layer, forming second residual etch stop layer and a second hard mask pattern which cover the second region, injecting a second impurities into the active fins of the first region, and removing the second residual etch stop layer and the second hard mask pattern.

Abstract: An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap.

Abstract: A field effect transistor includes a first substrate region having a channel region and a second substrate region where a heavily doped region is formed. The channel region includes a first portion having a first width and a second portion having a second width larger than the first width. Related fabrication methods are also described.

Abstract: An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap.

Abstract: An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap.

Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film Is interposed between the gate and the PEOX film in the main chip region.

Abstract: A semiconductor device may include an active region of a semiconductor substrate and first and second impurity regions in the active region. The active region may have a first conductivity type, the first and second impurity regions may have a second conductivity type opposite the first conductivity type, and the first and second impurity regions are spaced apart to define a channel region therebetween. A first source/drain region may be provided in the first impurity region, a second source/drain region may be provide in the second impurity region, the first and second source/drain regions may have the second conductivity type, and impurity concentrations of the first and second source/drain regions may be greater than impurity concentrations of the first and second impurity regions.

Abstract: A field effect transistor includes a first substrate region having a channel region and a second substrate region where a heavily doped region is formed. The channel region includes a first portion having a first width and a second portion having a second width larger than the first width. Related fabrication methods are also described.

Abstract: An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region.

Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film Is interposed between the gate and the PEOX film in the main chip region.

Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film is interposed between the gate and the PEOX film in the main chip region.

Abstract: A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film is interposed between the gate and the PEOX film in the main chip region.

Abstract: A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. The trench region has a deep trench region where the upper silicon layer penetrates to the buried insulating layer and a shallow trench region existing at an outside of the deep trench region. The method of forming a trench region with deep and shallow trench regions includes patterning an upper silicon layer of an SOI substrate. A trench oxide layer and a trench liner are conformally formed on a sidewall and a bottom of the trench region.