Abstract: Disclosed herein is a composition for molecular imaging comprising a trans-splicing ribozyme coupled with an imaging reporter gene. The trans-splicing ribozyme targets a specific gene associated with a disease. Also disclosed is a molecular imaging method using the composition.

Abstract: A semiconductor device includes contact plugs formed in contact holes defined in an interlayer dielectric. Upper portions of the contact plugs are etched. A first barrier layer is formed on a surface of the interlayer dielectric including the contact plugs. A second barrier layer is formed on the first barrier layer over the interlayer dielectric. The second barrier layer has lower compatibility with a metallic material than the first barrier layer. A first metal layer is formed over the first and second barrier layers. The first metal layer, the first barrier layer and the second barrier layer are then patterned.

Abstract: The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.

Abstract: A light absorbent for forming an organic anti-reflective layer, represented by the following formula 1 or formula 2, is provided: wherein A represents a substituted or unsubstituted, linear or branched, saturated tetravalent hydrocarbon group, a substituted or unsubstituted, linear or branched, saturated hydrocarbon group and containing one or more heteroatoms, a substituted or unsubstituted aromatic group, a substituted or unsubstituted heteroaromatic group, a substituted or unsubstituted alicyclic group, a substituted or unsubstituted heteroalicyclic group, a substituted or unsubstituted diaryl ether, a substituted or unsubstituted diaryl sulfide, a substituted or unsubstituted diaryl sulfoxide, a substituted or unsubstituted diaryl ketone, or a substituted or unsubstituted diaryl bisphenol A; R1, R2, and R3 each independently represent a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group a substituted or unsubstituted aryl group, a substituted or unsubstituted acetal group, o

Abstract: A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is deposited with a method having selectivity with respect to the same material as the first conductive layer, thus fully filling the contact holes. A metal line is formed on the second conductive layer. The contact holes are completely filled with a conductive material and the load of a CMP process can be alleviated. Accordingly, the electrical characteristics of a device can be improved, process reliability can be improved, and process repeatablity can be improved.

Abstract: The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface including the trenches. A metal layer is formed on the diffusion barrier layer including the trenches, thereby gap-filling the trenches. A polish etching process is performed on the metal layer and the diffusion barrier layer so that the diffusion barrier layer and the metal layer remain within the trenches. An etching process of lowering a height of the metal layer is performed in order to increase a distance between metal lines. A capping layer is formed on the entire surface including exposed sidewalls of the first pre-metal dielectric layer. A second pre-metal dielectric layer is formed over the capping layer.

Abstract: A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.

Abstract: A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.

Abstract: Disclosed herein is a method of forming a metal line of a semiconductor device. According to the method, a contact hole is formed in a second insulating layer over a semiconductor substrate. A first barrier metal layer, including a TiN layer, is formed on a surface of the second insulating layer. The first barrier metal layer is formed such that the TiN layer is formed thinner at a bottom of the contact hole than on sidewalls and a top surface of the second insulating layer. A first metal layer is formed on the first barrier metal layer, including on the contact hole. Thermal treatment is carried to gap-fill the contact hole as the first metal layer is reflown and smooth. A second metal layer is formed on the first metal layer. The second metal layer to form an upper metal line.

Abstract: A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.

Abstract: A method of manufacturing a non-volatile memory device includes forming a trench using the shallow trench isolation (STI) method; forming a first insulating layer on a semiconductor device including the trench; forming a conductive layer on the semiconductor device including the trench; etching the conductive layer to form a conductive layer for a floating gate on an active area and to form a recessed gap-fill conductive layer on an isolation layer; forming a second insulating layer and a third insulating layer on the semiconductor substrate including the gap fill conductive layer and the conductive layer for the floating gate; and etching a portion of the second insulating layer and the third insulating layer to form an isolation structure consisting of the gap fill conductive layer, the second insulating layer and the third insulating layer on the isolation area.

Abstract: A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

Abstract: According to a method of forming a metal wiring of a semiconductor device, a contact plug is formed at height lower than the contact hole, which is formed on an interlayer insulation layer, and then a metal wiring is formed over the contact plug and interlayer insulation layer to completely fill inside of the contact hole, decreasing process difficulty, ensuring reproducibility, and improving electrical property.

Abstract: A semiconductor device includes contact plugs formed in contact holes defined in an interlayer dielectric. Upper portions of the contact plugs are etched. A first barrier layer is formed on a surface of the interlayer dielectric including the contact plugs. A second barrier layer is formed on the first barrier layer over the interlayer dielectric. The second barrier layer has lower compatibility with a metallic material than the first barrier layer. A first metal layer is formed over the first and second barrier layers. The first metal layer, the first barrier layer and the second barrier layer are then patterned.

Abstract: A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material.

Abstract: A method of forming a contact plug in a semiconductor device comprising etching an interlayer insulating layer to form a patterned interlayer insulating layer having contact holes such that a distance between upper portions of the contact holes is minimized; forming a first insulating layer including a overhang portion for wrapping an upper portion of the patterned interlayer insulating layer; forming a liner-shaped second insulating layer on the patterned interlayer insulating layer including the first insulating layer, the second insulating layer being formed from material having a selectivity which differs from that of the first insulating layer; and at least partially removing the second insulating layer to increase a bottom critical dimension of the contact hole and removing the overhang portion of the first insulating layer.

Abstract: A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.

Abstract: The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.

Abstract: The present invention relates to a semiconductor device and a method of fabricating the same. In an embodiment of the present invention, an insulating layer in which contact holes are formed is formed over a semiconductor substrate in which lower metal lines are formed. A barrier metal layer, having a stack structure of a first tungsten (W) layer and a tungsten nitride (WN) layer, is formed within the contact holes. Contact plugs are formed within the contact holes.

Abstract: A metal line of a semiconductor device includes an insulating layer in which damascene patterns have been formed, a first metal layer formed on sidewalls and bottom surfaces of the damascene patterns, a second metal layer formed on the first metal layer within the damascene patterns and having a lower resistance than the first metal layer, and a third metal layer formed on the second metal layer.