Patents by Inventor Seung-hee KO
Seung-hee KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951938Abstract: A steering wheel locking control apparatus may include: a power supply switch configured to receive power from a battery when an ignition switch of a vehicle is turned off; and a switch unit connected to a motor, turned on when power is received through the power supply switch, and configured to lock a steering wheel through a closed circuit formed by shorting phases of the motor.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: Hyundai Mobis Co., Ltd.Inventors: Jung Suk Ko, Sung Ho Jang, Seung Young Park, Hyeon Hee Jeong
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Publication number: 20240090280Abstract: A display device includes a display panel including a main area and a sensor area. Sensor devices overlap the sensor area of the display panel in a thickness direction of the display panel. The display panel includes first subpixels, which are disposed in the sensor area, and second subpixels, which are disposed in the main area. The number of transistors of each of the first subpixels is different from the number of transistors of each of the second subpixels.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: SEUNG CHAN LEE, Gun Hee Kim, Sung Jin Hong, Yoo Min Ko
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Patent number: 11011807Abstract: A coupling frame includes a support body configured to contact at least one of the electrode tab and the electrode lead; a first perforating portion bent from one end of the support body; and a second perforating portion bent from the other end of the support body. The first and second perforating portions are inserted into the electrode tab and the electrode lead to pass through first and second points of a contact surface between the electrode tab and the electrode lead.Type: GrantFiled: February 2, 2018Date of Patent: May 18, 2021Inventors: Seung-Hee Ko, Jae-Bin Chung
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Publication number: 20180219207Abstract: A coupling frame includes a support body configured to contact at least one of the electrode tab and the electrode lead; a first perforating portion bent from one end of the support body; and a second perforating portion bent from the other end of the support body. The first and second perforating portions are inserted into the electrode tab and the electrode lead to pass through first and second points of a contact surface between the electrode tab and the electrode lead.Type: ApplicationFiled: February 2, 2018Publication date: August 2, 2018Inventors: Seung-Hee Ko, Jae-Bin Chung
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Patent number: 9530729Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.Type: GrantFiled: September 21, 2015Date of Patent: December 27, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-gyu Choi, Hyun-chul Kim, Seung-hee Ko
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Publication number: 20160013131Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Yong-gyu Choi, Hyun-chul Kim, Seung-hee Ko
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Patent number: 9184091Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.Type: GrantFiled: December 10, 2013Date of Patent: November 10, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bo-Young Song, Cheol-Ju Yun, Seung-Hee Ko, Jina Kim, Hyun-Gi Kim, Chae-Ho Lim
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Patent number: 9165934Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.Type: GrantFiled: July 29, 2014Date of Patent: October 20, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-gyu Choi, Hyun-chul Kim, Seung-hee Ko
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Publication number: 20150171420Abstract: Disclosed are a negative active material for a rechargeable lithium battery including a core including a material being capable of intercalating and deintercalating lithium ions and a shell positioned on the surface of the core, wherein the shell includes antimony-doped tin oxide, a method of manufacturing the same, and a rechargeable lithium battery including the same.Type: ApplicationFiled: March 27, 2014Publication date: June 18, 2015Applicants: SEJIN INNOTECH CO., LTD., UNIST Academy-Industry Research CorporationInventors: Soojin PARK, Sang-Young Lee, Seung Hee Ko, Jung-In Lee, Jang-Hoon Park, Han Ho Lee, Ji Hyun Yoon, Byoung Man Bang, Chang Rae Lee, Il Kyo Jeong
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Patent number: 8987860Abstract: A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.Type: GrantFiled: December 11, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-young Song, Cheol-ju Yun, Seung-hee Ko
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Publication number: 20150061154Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.Type: ApplicationFiled: July 29, 2014Publication date: March 5, 2015Inventors: Yong-Gyu Choi, Hyun-Chul Kim, Seung-hee Ko
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Patent number: 8946077Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.Type: GrantFiled: January 17, 2014Date of Patent: February 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeon-Kyu Lee, Bo-Young Song, Seung-Hee Ko, Jin-A Kim, Hyun-Gi Kim, Cheol-Ju Yun, Chae-Ho Lim
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Publication number: 20140231892Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.Type: ApplicationFiled: December 10, 2013Publication date: August 21, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Bo-Young SONG, Cheol-Ju YUN, Seung-Hee KO, Jina KIM, Hyun-Gi KIM, Chae-Ho LIM
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Publication number: 20140206186Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.Type: ApplicationFiled: January 17, 2014Publication date: July 24, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeon-Kyu Lee, Bo-Young Song, Seung-Hee Ko, Jin-A Kim, Hyun-Gi Kim, Cheol-Ju Yun, Chae-Ho Lim
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Publication number: 20140159194Abstract: A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.Type: ApplicationFiled: December 11, 2013Publication date: June 12, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bo-young SONG, Cheol-ju YUN, Seung-hee KO