Abstract: A novel strain, Lactobacillus paracasei ATG-E1 (Accession No. KCTC 14245BP), and a composition containing the same for preventing or treating respiratory diseases which are caused by fine particulate matter. The Lactobacillus paracasei ATG-E1 strain reduces the number of immune cells bronchoalveolar and lung tissues and inhibits the expression of inflammatory cytokines such as interleukin-17A (IL-17A), tumor necrosis factor-? (TNF-?), macrophage inflammatory protein 2 (MIP2), C-X-C motif chemokine ligand 1 (CXCL-1), macrophage inflammatory protein-? (MIP-1?) or interleukin-6 (IL-6).

Abstract: A display device includes a display panel including a main area and a sensor area. Sensor devices overlap the sensor area of the display panel in a thickness direction of the display panel. The display panel includes first subpixels, which are disposed in the sensor area, and second subpixels, which are disposed in the main area. The number of transistors of each of the first subpixels is different from the number of transistors of each of the second subpixels.

Abstract: A banking processing method according is performed by a processing logic including an application for banking processing implemented on a user terminal and a computer-readable storage medium. The method comprises the steps of: when the application for banking processing is run, searching a hardware security area of the user terminal and confirming the existence of a certificate for confirming an execution history of the application for banking processing; when the existence of the certificate is confirmed, searching the security area and confirming the existence of a token key for identifying whether login information of the user has been set; when the existence of the token key is not confirmed, setting the login information of the user by providing a membership page for setting the login information of the user; and opening an account according to a request of the user whose login information has been set.

Abstract: Proposed is a method for providing an emoticon input interface by a user terminal. The method may include displaying a first input interface for inputting an emoticon to be posted on a profile page of a user. The method may also include receiving a selection interaction of selecting a first emoticon to be posted on the profile page of the user via the first input interface, and displaying the selected first emoticon on the profile page of the user. The first input interface may include user custom information associated with emoticon historical information of the user. The user custom information may be identical to at least a part of user custom information for a second input interface for inputting an emoticon to be displayed in a chat message.

Abstract: A coupling frame includes a support body configured to contact at least one of the electrode tab and the electrode lead; a first perforating portion bent from one end of the support body; and a second perforating portion bent from the other end of the support body. The first and second perforating portions are inserted into the electrode tab and the electrode lead to pass through first and second points of a contact surface between the electrode tab and the electrode lead.

Abstract: A coupling frame includes a support body configured to contact at least one of the electrode tab and the electrode lead; a first perforating portion bent from one end of the support body; and a second perforating portion bent from the other end of the support body. The first and second perforating portions are inserted into the electrode tab and the electrode lead to pass through first and second points of a contact surface between the electrode tab and the electrode lead.

Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.

Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.

Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.

Abstract: Disclosed are a negative active material for a rechargeable lithium battery including a core including a material being capable of intercalating and deintercalating lithium ions and a shell positioned on the surface of the core, wherein the shell includes antimony-doped tin oxide, a method of manufacturing the same, and a rechargeable lithium battery including the same.

Abstract: A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.

Abstract: A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract: A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.