Abstract: An antenna apparatus includes: a parabolic reflector; a dielectric support pedestal; a sub-reflector connected to an upper part of the dielectric support pedestal; and a waveguide connected to a lower part of the dielectric support pedestal, wherein the parabolic reflector has a curved surface in which a ratio of a focal length to a diameter is greater than a preset value, and at least one corrugation configured to suppress a cross polarization is formed in a region of the dielectric support pedestal.

Abstract: An apparatus and method for treating a substrate are provided. The apparatus includes at least one first process chamber configured to supply a developer onto the substrate; at least one second process chamber configured to treat the substrate using a supercritical fluid; a transfer chamber configured to transfer the substrate from the at least one first process chamber to the at least one second process chamber, while the developer supplied in the at least one first process chamber remains on the substrate; and a temperature and humidity control system configured to manage temperature and humidity of the transfer chamber by supplying a first gas of constant temperature and humidity into the transfer chamber.

Abstract: A gate driver may include: a controller to charge and discharge a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; a first output unit having a first pull-up transistor to apply a gate high voltage to an output node in response to a charging voltage of the first control node, and a first pull-down transistor to apply a gate low voltage to the output node in response to a charging voltage of the second control node; and a switch unit to change a current path between a first output node and a first power line to which a high potential voltage is applied or a second power line to which a first clock signal is applied according to a carry signal transmitted from a previous signal transmission unit and a voltage level of the second control node.

Abstract: A gate driver includes a first shift register to supply a gate signal to a plurality of gate lines through output nodes, and a second shift register to supply the gate signal to the gate lines through output nodes. The gate signal is supplied from the first shift register to one side of an i-th gate line and supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the first shift register to one side of the i-th gate line, and then, the gate signal is supplied from the first shift register to one side of the i-th gate line and simultaneously supplied from the second shift register to the other side of the i-th gate line.

Abstract: A gate driving circuit according to an embodiment and a display panel including the same are disclosed. The gate driving circuit according to the embodiment includes: a controller configured to charge and discharge a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; an output unit including a pull-up transistor configured to apply a gate high voltage to an output node in response to a charging voltage of the first control node, and a pull-down transistor configured to apply a gate low voltage to the output node in response to a charging voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; and a compensation unit configured to change the charging voltage of the second control node in response to an output of the sensing unit.

Abstract: A pixel circuit and a display device including the same are disclosed. The pixel circuit includes: a first driving element including a first electrode connected to a 1-1 th node, a gate electrode connected to a 1-2 th node, and a second electrode connected to a 1-3 th node; and a second driving element including a first electrode connected to a 2-1 th node, a gate electrode connected to a 2-2 th node, and a second electrode connected to a second-third node. A second electrode voltage of the first driving element is transmitted to the gate electrode of the second driving element, and a second electrode voltage of the second driving element is transmitted to the gate electrode of the first driving element.

Abstract: Disclosed are a pixel circuit and a display device including the same. The pixel circuit includes a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switch element including a first electrode connected to a fourth node, a gate electrode to which a scan pulse is applied, and a second electrode connected to the first node, and configured to be turned on according to a gate-on voltage of the scan pulse while a threshold voltage of the driving element is sensed; and a first capacitor connected between the second node and the fourth node.

Abstract: A gate driver may include: a controller to charge and discharge a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; a first output unit having a first pull-up transistor to apply a gate high voltage to an output node in response to a charging voltage of the first control node, and a first pull-down transistor to apply a gate low voltage to the output node in response to a charging voltage of the second control node; and a switch unit to change a current path between a first output node and a first power line to which a high potential voltage is applied or a second power line to which a first clock signal is applied according to a carry signal transmitted from a previous signal transmission unit and a voltage level of the second control node.

Abstract: A pixel circuit and a display device including the same are disclosed. The pixel circuit includes: a first driving element including a first electrode connected to a 1-1 th node, a gate electrode connected to a 1-2 th node, and a second electrode connected to a 1-3 th node; and a second driving element including a first electrode connected to a 2-1 th node, a gate electrode connected to a 2-2 th node, and a second electrode connected to a second-third node. A second electrode voltage of the first driving element is transmitted to the gate electrode of the second driving element, and a second electrode voltage of the second driving element is transmitted to the gate electrode of the first driving element.

Abstract: A gate driving circuit according to an embodiment and a display panel including the same are disclosed. The gate driving circuit according to the embodiment includes: a controller configured to charge and discharge a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; an output unit including a pull-up transistor configured to apply a gate high voltage to an output node in response to a charging voltage of the first control node, and a pull-down transistor configured to apply a gate low voltage to the output node in response to a charging voltage of the second control node; a sensing unit configured to sense a threshold voltage of the pull-down transistor; and a compensation unit configured to change the charging voltage of the second control node in response to an output of the sensing unit.

Abstract: A gate driver includes a first shift register to supply a gate signal to a plurality of gate lines through output nodes, and a second shift register to supply the gate signal to the gate lines through output nodes. The gate signal is supplied from the first shift register to one side of an i-th gate line and supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the first shift register to one side of the i-th gate line, and then, the gate signal is supplied from the first shift register to one side of the i-th gate line and simultaneously supplied from the second shift register to the other side of the i-th gate line.

Abstract: Disclosed are a pixel circuit and a display device including the same. The pixel circuit includes a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switch element including a first electrode connected to a fourth node, a gate electrode to which a scan pulse is applied, and a second electrode connected to the first node, and configured to be turned on according to a gate-on voltage of the scan pulse while a threshold voltage of the driving element is sensed; and a first capacitor connected between the second node and the fourth node.

Abstract: Provided are a gate driving circuit and a display device including the same. The gate driving circuit includes a first controller configured to control a first control node to act as a pull-up control node to turn on a first transistor when an activation clock is input to the first controller for a first unit time, and to be deactivated when a deactivation clock is input thereto for a second unit time; and a second controller configured to control a second control node to act as a pull-up control node to turn on a second transistor when the activation clock is input to the second controller for the second unit time, and to be deactivated when the deactivation clock is input thereto for the first unit time.

Abstract: Disclosed is a light emitting display device which may prevent or at least reduce lateral leakage current. The light emitting display device includes a substrate comprising a plurality of first to third subpixels arranged to neighbor one another, each of the first to third subpixels comprising an emission part and a non-emission part to surround the emission part; a bank at the non-emission parts; first electrodes covered with the bank and respectively at the first to third subpixels to expose the respective emission parts; a first spacer structure having an inversed tapered shape configured to surround at least one side of each of the emission parts of the first to third subpixels on the bank; a common layer structure located on the first electrodes and the first spacer structure and disconnected at an edge of the first spacer structure; and a second electrode on the common layer structure.

Abstract: Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal.

Abstract: A liquid crystal panel with an improved picture-quality and an LCD device having the same are disclosed. The liquid crystal panel and the LCD device allows a distance between a pixel electrode and a data line not connected to a thin film transistor and another distance between the pixel electrode and another data line to be asymmetrically formed within a single pixel region. Accordingly, the vertical cross-talk can be minimized, and furthermore picture-quality can be improved.

Abstract: Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal.

Abstract: A liquid crystal display device includes a plurality of pixels at intersections of a plurality of row lines and a plurality of column lines, wherein each pixel includes a switching transistor, and pixel and common electrodes that induce an in-plane electric field; a plurality of gate lines each connected to the pixels on each row line; a plurality of data lines each connected to the pixels on each column line; and a plurality of common lines each connected to the common electrodes of the pixels alternately located on neighboring two row lines per one column line.

Abstract: A thin film transistor array substrate includes a gate line provided on a substrate, a data line crossing the gate line to define a pixel area, a gate insulating film between the gate line and the data line at the crossing of the gate line and data line, a thin film transistor adjacent to the crossing of the gate line and the data line, a protective film covering the thin film transistor, a pixel electrode on the pixel area and electrically connected to a drain electrode of the thin film transistor, a gate pad connected to the gate line, a data pad connected to the data line, a lower data link electrode connected to the data line, an upper data link electrode connected to the data line and overlapping one end of the lower data link electrode, and a link electrode connecting the lower data link electrode via a first contact hole passing through the protective film and the gate insulating film at a first area of the substrate in which the protective film is directly provided on the gate insulating film.

Abstract: A liquid crystal display device includes a plurality of pixels at intersections of a plurality of row lines and a plurality of column lines, wherein each pixel includes a switching transistor, and pixel and common electrodes that induce an in-plane electric field; a plurality of gate lines each connected to the pixels on each row line; a plurality of data lines each connected to the pixels on each column line; and a plurality of common lines each connected to the common electrodes of the pixels alternately located on neighboring two row lines per one column line.