Abstract: A battery pack includes a battery module assembly having at least one battery cell, a pack case configured to accommodate the battery module assembly, and a barrier unit provided on at least one side of the pack case, configured to discharge a vent gas in the pack case to the outside of the pack case and having at least one blocking baffle disposed obliquely to have a predetermined inclination angle.

Abstract: A battery pack includes a plurality of battery modules each including one or more battery cells to store and release energy, each battery module further including an intake portion and an exhaust portion, an intake duct including an intake channel and communicating with the intake portion of each of the plurality of battery modules, and an exhaust duct including an exhaust channel and communicating with the exhaust portion of each of the plurality of battery modules. Each of the plurality of battery modules further includes an opening/closing member configured to close the intake portion when internal pressure increases.

Abstract: A battery pack is configured to improve safety by effectively suppressing heat transfer between battery modules in the present disclosure. A battery pack includes a plurality of battery modules each having one or more battery cells, configured to store and release energy, and stacked in at least one direction; a pack case provided on at least one side of the plurality of battery modules, covering at least a portion of the outside of the plurality of battery modules, and having one or more openings formed therein; and a melting member provided in the opening of the pack case to seal the opening and configured to open the opening by being melted by heat generated from one or more battery modules among the plurality of battery modules.

Abstract: A battery rack includes a plurality of battery modules, each including at least one battery cell, wherein each battery module has at least one venting hole; a rack case accommodating the plurality of battery modules; and a plurality of support brackets disposed in the rack case such that each support bracket supports each battery module and is in communication with the at least one venting hole.

Abstract: A battery module ac includes a cell stack in which a plurality of battery cells are vertically stacked; a module housing including a base plate supporting the cell stack, and a pair of side plates covering both side portions of the cell stack and each including a spark direction changing portion formed by bending an end portion of the side plate in a longitudinal direction of the side plate toward the cell stack; and a bus bar frame assembly covering an opening portion formed on a side of the module housing in a longitudinal direction of the module housing, the bus bar frame assembly including a bus bar frame coupled to a side of the cells tack in a longitudinal direction of the cell stack and a bus bar located on the bus bar frame and coupled to an electrode lead of the battery cell.

Abstract: A battery module includes a cell stack in which a plurality of battery cells are vertically stacked; a module housing including a base plate supporting the cell stack and a pair of side plates covering both side portions of the cell stack; a bus bar frame assembly covering an opening portion formed on a side of the module housing in a longitudinal direction of the module housing; and a plurality of spark delay portions protruding from an inner surface of each of the pair of side plates and spaced apart from one another in a height direction of the side plate.

Abstract: A battery pack includes a sub-pack including a plurality of battery modules that are located adjacent to one another; a duct coupled to a side of the sub-pack in a width direction of the sub-pack; and a duct cover covering a duct opening portion formed on a side of the duct in a longitudinal direction of the duct, the duct cover including a filter having a mesh structure.

Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

Abstract: An input/output circuit for a memory and a method of controlling the same are disclosed. The input/output circuit and the method of controlling the same are configured to prevent a memory element from being falsely or incorrectly programmed due to an ESD pulse. More particularly, the input/output circuit and the method of controlling the same include an ESD detection unit configured to detect a programming voltage or an ESD pulse on a pad terminal, a control logic unit configured to transmit a first voltage or a second voltage according to the programming voltage and the ESD pulse, and a switch unit configured to perform a turn-on or turn-off operation according to the first voltage or the second voltage.

Abstract: An ESD protection circuit for an input/output buffer in which when an ESD pulse or event occurs, an ESD surge on a pad is discharged to a diode and a transistor channel, thereby enhancing the efficiency of the ESD protection circuit. The ESD protection circuit includes a floating N-well bias circuit connected to a pad at an output of driver circuit and outputting a bias voltage based on or in response to a supply voltage; a switch circuit connected to a logic circuit and the driver circuit, and configured to connect and disconnect the logic circuit and the driver circuit based on or in response to the supply voltage; and a pull-down circuit connected to the driver circuit, configured to output a voltage to the driver circuit based on or in response to the supply voltage.

Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

Abstract: A voltage on-off detector includes an inverter between a first voltage source and a third voltage source providing a third voltage and having an input terminal that receives a second voltage, a first transistor having a gate that receives the second voltage, and a first source and a first drain between the third voltage source and a first node, a second transistor having a second gate that receives the third voltage, and a second source and a second drain between a second voltage source providing the second voltage and the first node, and an amplifier configured to output a first voltage from the first voltage source or a voltage on the first node based on or in response to an output of the inverter.

Abstract: An ESD protection circuit for an input/output buffer in which when an ESD pulse or event occurs, an ESD surge on a pad is discharged to a diode and a transistor channel, thereby enhancing the efficiency of the ESD protection circuit. The ESD protection circuit includes a floating N-well bias circuit connected to a pad at an output of driver circuit and outputting a bias voltage based on or in response to a supply voltage; a switch circuit connected to a logic circuit and the driver circuit, and configured to connect and disconnect the logic circuit and the driver circuit based on or in response to the supply voltage; and a pull-down circuit connected to the driver circuit, configured to output a voltage to the driver circuit based on or in response to the supply voltage.

Abstract: A voltage on-off detector includes an inverter between a first voltage source and a first node and having an input terminal that receives a third voltage, a first transistor having a first gate, and a first source and a first drain between the first node and a second voltage source, a second transistor having a second source connected to the second voltage source, and a second gate and a second drain connected to the first node, and an amplifier having an input terminal connected to an output terminal of the inverter and configured to output a first voltage from the first voltage or a second voltage from the second voltage source based on or in response to an output of the inverter.

Abstract: An input/output circuit includes a logic unit configured to generate a first signal and a second signal based on data and a first control signal, a driver including a first PMOS transistor having a first gate, a first source that receives a first voltage from a first voltage source, and a first drain, and a first NMOS transistor having a second gate that receives the second signal, a second source that receives a second voltage from a second voltage source less than the first voltage, and a second drain connected to the first drain, a gate-tracking circuit configured to receive the first signal and transfer the received first signal to the first gate of the first PMOS transistor based on a second control signal, and an input/output terminal connected to the first drain and the second drain.