Patents by Inventor Seung Hoon Hoon SUNG

Seung Hoon Hoon SUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9698222
    Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Sherry R. Taft, Van H. Le, Sansaptak Dasgupta, Seung Hoon Hoon Sung, Sanaz K. Gardner, Matthew V. Metz, Marko Radosavljevic, Han Wui Then
  • Patent number: 9660085
    Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 23, 2017
    Assignee: Intel Coporation
    Inventors: Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Seung Hoon Hoon Sung, Sanaz K. Gardner, Ravi Pillarisetty
  • Publication number: 20160308041
    Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transitors and other transistors can form.
    Type: Application
    Filed: December 23, 2013
    Publication date: October 20, 2016
    Inventors: Han Wui Then, Robert S. CHAU, Sansaptak DASGUPTA, Marko RADOSAVLJEVIC, Benjamin CHU-KUNG, Seung Hoon Hoon SUNG, Sanaz K. GARDNER, Ravi PILLARISETTY
  • Publication number: 20160276438
    Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.
    Type: Application
    Filed: December 23, 2013
    Publication date: September 22, 2016
    Inventors: Benjamin CHU-KUNG, Sherry R. TAFT, Van H. LE, Sansaptak DASGUPTA, Seung Hoon Hoon SUNG, Sanaz K. GARDNER, Matthew V. METZ, Marko RADOSAVLJEVIC, Han Wui THEN