Patents by Inventor Seunghun WANG

Seunghun WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220158588
    Abstract: An electronic circuit according to various embodiments may comprise: a switch circuit, wherein the switch circuit may comprise: a first switch connected to a first port and a second switch connected to a second port, the first and second switches being connected in series with each other; a first parallel switch connected to a node between the first switch and the second switch; and a first shunt inductor connected to the node between the first switch and the second switch and configured to cancel a parasitic capacitance component of the first parallel switch.
    Type: Application
    Filed: February 11, 2020
    Publication date: May 19, 2022
    Inventors: Sungku YEO, Seunghun WANG, Songcheol HONG, Jaeseok PARK, Jinseok PARK, Chongmin LEE
  • Patent number: 10659021
    Abstract: A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 19, 2020
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Sungku Yeo, Gwanghyeon Jeong, Songcheol Hong, Jaeseok Park, Seunghun Wang, Youngho Ryu, Junhan Lim
  • Publication number: 20190222205
    Abstract: A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.
    Type: Application
    Filed: January 15, 2019
    Publication date: July 18, 2019
    Inventors: Sungku YEO, Gwanghyeon JEONG, Songcheol HONG, Jaeseok PARK, Seunghun WANG, Youngho RYU, Junhan LIM