Abstract: An operating method of a semiconductor memory device includes performing a first read operation on main cells of a first page with an initial read voltage, performing a second read operation on the main cells of the first page with a read voltage corresponding to a read retry number when the number of error bits generated as results of performing the first read operation exceeds the number of error-correctable bits, and storing the read retry number in spare cells of the first page while the second read operation is performed, and repeatedly performing the second read operation and repeatedly storing the read retry number until the number of error bits generated as results of performing the second read operation becomes the number of error-correctable bits or less.

Abstract: A wheel bearing assembly includes an outer race in which a plurality of rows of track portions are formed at an inner side thereof; a hub that is coaxially disposed with the outer race to be rotatably disposed in the outer race; an inner race that is engaged with a portion of an outside surface of the hub to rotate together with the hub; a first roller that is interposed between the hub and the outer race to be rolled; and a second roller that is interposed between the inner race and the outer race to be rolled.

Abstract: A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.

Abstract: A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.

Abstract: The present invention discloses a wheel bearing assembly according to an exemplary embodiment of the present invention may include: an outer race in which a plurality of rows of track portions are formed at an inner side thereof; a hub that is coaxially disposed with the outer race to be rotatably disposed in the outer race; an inner race that is engaged with one side outside surface of the hub to rotate together with the hub; and rollers that are interposed between the hub and the outer race and between the inner race and the outer race to be rolled.

Abstract: An operating method of a semiconductor memory device includes performing a first read operation on main cells of a first page with an initial read voltage, performing a second read operation on the main cells of the first page with a read voltage corresponding to a read retry number when the number of error bits generated as results of performing the first read operation exceeds the number of error-correctable bits, and storing the read retry number in spare cells of the first page while the second read operation is performed, and repeatedly performing the second read operation and repeatedly storing the read retry number until the number of error bits generated as results of performing the second read operation becomes the number of error-correctable bits or less.

Abstract: A method of operating a semiconductor memory device includes an operation of applying a first voltage to selected bit lines, a second voltage to unselected bit lines and a common source line, and turning on drain and source selection transistors, an operation of applying a program voltage to a selected word line and a switch voltage to a switch word line, and applying a first pass voltage to first unselected word lines disposed between the switch word line and a common source line and between the selected word line and a bit line, and elevating the switch voltage to generate hot electrons and inject the hot electrons to a selected memory cell of the selected word line to program the selected cell.

Abstract: A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the first target level as a first target level, and the second memory cells having a second target level higher than the first target level as a second target level; performing a second program operation on the second memory cells so that the threshold voltages of the second memory cells have a second reference level lower than the second target level; and performing a third program operation on the first and second memory cells to have the respective target levels.

Abstract: A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the first target level as a first target level, and the second memory cells having a second target level higher than the first target level as a second target level; performing a second program operation on the second memory cells so that the threshold voltages of the second memory cells have a second reference level lower than the second target level; and performing a third program operation on the first and second memory cells to have the respective target levels.

Abstract: A first verify voltage is applied to a word line of a selected memory cell, after a bit line is precharged, to program-verify the memory cell in a nonvolatile memory device. A first read evaluation operation for changing a voltage of the bit line is performed. Results of the first read evaluation operation are sensed using a first sensing voltage. A second read evaluation operation for changing the voltage of the bit line is performed again. Results of the second read verify operation are then sensed using the first sensing voltage.

Abstract: A first verify voltage is applied to a word line of a selected memory cell, after a bit line is precharged, to program-verify the memory cell in a nonvolatile memory device. A first read evaluation operation for changing a voltage of the bit line is performed. Results of the first read evaluation operation are sensed using a first sensing voltage. A second read evaluation operation for changing the voltage of the bit line is performed again. Results of the second read verify operation are then sensed using the first sensing voltage.

Abstract: A first verify voltage is applied to a word line of a selected memory cell, after a bit line is precharged, to program-verify the memory cell in a nonvolatile memory device. A first read evaluation operation for changing a voltage of the bit line is performed. Results of the first read evaluation operation are sensed using a first sensing voltage. A second read evaluation operation for changing the voltage of the bit line is performed again. Results of the second read verify operation are then sensed using the first sensing voltage.