Abstract: An LCD corrects deviations in pixel kickback voltages caused by delays in gate driving signals. The LCD includes a timing controller generating first and second output enable signals, first and second level shifters respectively generating first and second gate clock pulses and inverted clock pulses, and first and second gate drivers respectively generating first and second gate driving signals. A precharge time of the first gate driving signals is controlled by the pulse width of the first output enable signal and a precharge time of the second gate driving signals is controlled by the pulse width of the second output enable signal.

Abstract: A liquid crystal display apparatus includes a liquid crystal panel assembly having pixels arranged in a matrix form, which have a first group of pixels and a second group of pixels, gate lines having a first group of gate lines and a second group of gate lines that are connected with the first group of pixels and the second group of pixels, respectively, and data lines each of which is connected with one of the first group of pixels and one of the second group of pixels in every row of the matrix form. The liquid crystal display apparatus also includes a signal controller that receives input image signals and generates two groups of image data, a data driver that receives the two groups of image data and provides data voltages corresponding to the image data to the data lines, and a gate driving unit including a first gate driver that provides first gate-on signals to the first group of gate lines and a second gate driver that provides second gate-on signals to the second group of gate lines.

Abstract: An LCD with an integrated touch panel that prevents sensor malfunction by eliminating coupling noises includes an insulating substrate, a plurality of gate lines formed on the insulating substrate so as to extend in a first direction, a plurality of data lines formed in a second direction so as to intersect the plurality of gate lines, a plurality of thin film transistors (TFTs), each formed at an area defined by the gate lines and the data lines, a plurality of sensor lines formed in the same directions as the gate lines and the data lines, and a plurality of dummy lines formed in the same directions as the sensor lines.

Abstract: A display apparatus that can conserve power without compromising general display quality is presented. In a display system including a main control apparatus and a display apparatus, the main control apparatus generates an image control signal having an image data, and a main clock signal that changes from a first frequency to a second frequency in response to a change in image mode from a first image mode to a second image mode. The change from the first frequency to the second frequency includes changing through at least one intermediate frequency stage between the first frequency and the second frequency. By maintaining the change of frequency shift small (i.e., less than a predetermined maximum change), operation in emergency mode is avoided even when the frequency shift is sudden. The display apparatus receives the image control signal and the main clock signal to display an image.

Abstract: A liquid crystal display is provided, which includes: a liquid crystal panel including a gate line, a data line, and a pixel including a switching element connected to the gate line and the data line; a gate driver applying a gate signal for controlling the switching element to the gate line; and a data driver selecting gray voltages corresponding to gray signals and applying the selected gray voltages to the data line. The gate signal includes a gate-on voltage for turning on the switching element and a gate-off voltage for turning off the switching element. The gray voltages include pairs of positive and negative voltages (V+, V?) and V + + V - 2 = Vconst for each gray, where Vconst indicates a predetermined level.

Abstract: A liquid crystal display, apparatus for driving a liquid crystal display and a method of driving gray voltages for the same. The liquid crystal display includes a plurality of gate lines transmitting gate signals, a plurality of data lines intersecting the plurality of gate lines and transmitting data voltages, and a plurality of pixel rows. Each pixel row includes a plurality of pixels, and each pixel includes a switching element connected to one of the plurality of gate lines and one of the plurality of data lines. The polarity of the data voltages supplied to the plurality of pixels are inverted by a pixel group including two or more pixel rows. The absolute values of the data voltages applied to one row of the pixel group with respect to a first predetermined voltage are greater than the absolute values of the data voltages applied to another row of the pixel group for the same grays.

Abstract: Disclosed is an LCD apparatus having improved display characteristics. A clock generator applies first and second clock signals to a gate driver so as to control a pulse width of a gate driving signal. A discharging transistor connected to first ends of gate lines discharges a present stage before operating a next stage. The gate lines include a first gate driver and a second gate driver for operating the gate lines while the first gate driver is operated in an abnormal state. Accordingly, the LCD apparatus may be operated in high-speed and prevent the gate driving signal from being delayed.

Abstract: Disclosed is an LCD apparatus having improved display characteristics. A clock generator applies first and second clock signals to a gate driver so as to control a pulse width of a gate driving signal. A discharging transistor connected to first ends of gate lines discharges a present stage before operating a next stage. The gate lines include a first gate driver and a second gate driver for operating the gate lines while the first gate driver is operated in an abnormal state. Accordingly, the LCD apparatus may be operated in high-speed and prevent the gate driving signal from being delayed.

Abstract: A liquid crystal display includes a plurality of pixels arranged in a matrix, a substrate, and a plurality of gate lines, data lines, thin film transistors, pixel electrodes, and storage electrode lines. The gate lines are formed on the substrate. The data lines run crosswise relative to the gate lines above or below the gate lines, and the thin film transistors are connected to the gate lines and the data lines. The pixel electrodes are connected to the thin film transistors, and have a first side formed in parallel with the gate lines and a second side shorter than the first side and adjacent to the first side. The storage electrode lines overlap with the pixel electrodes. Storage electrode signals applied to the storage electrode lines are periodic alternating signals.

Abstract: An inverter driving apparatus for driving a plurality of lamp units is provided. The inverter driving apparatus includes a plurality of inverter boards for generating driving signals for driving respective lamp units based on a control signal and a voltage signal. Each lamp unit includes at least one lamp, and the plurality of inverter boards are connected in series and include a first outer inverter board receiving the control signal and a second outer inverter board located opposite the first outer inverter board receiving the voltage signal. Each of the plurality of inverter boards transmits the control signal and/or the voltage signal to at least one of the plurality of inverter boards adjacent thereto.

Abstract: An inverter apparatus for driving a plurality of lamp units including a plurality of lamps is provided. The inverter apparatus includes a plurality of inverters. Each inverter includes a delay block delaying an input ON/OFF signal to generate an output ON/OFF signal and an inverting block controlling the lighting of the corresponding lamp unit based on the output ON/OFF signal. The plurality of inverters includes a first inverter receiving the input ON/OFF signal from an external device and a second inverter receiving the input ON/OFF signal from one of the plurality of inverters.

Abstract: A shift register is provided, which includes: a plurality of stages sequentially outputting gate signals, each stage including: an input unit outputting a control signal based on an external signal; an output unit connected to the input unit and outputting a gate signal based on a first clock signal and the control signal; and a signal generating unit connected to the output unit and generating a transmission signal based on the first clock signal and the control signal.

Abstract: A shift register includes a plurality of stages each of which has a first pull-up driving part to generate a first control signal in response to an output signal of an adjacent previous stage or a control signal, a pull-up part to generate a current output signal in response to a first clock signal and the first control signal, a second pull-up driving part to generate at least one second control signal in response to the first clock signal and a second clock signal, a third pull-up driving part connected to a low level terminal to operate in response to an output signal of an adjacent following stage, and a pull-down part to operate in response to the second clock signal.

Abstract: A shift register has multiple stages each of which includes a pull-up part to generate a current gate line driving signal having a first state in response to a first control signal and a clock signal, a pull-down part to generate the current gate line driving signal having a second state in response to a second control signal, a pull-up driver to generate the first control signal to control the pull-up part in response to a previous gate line driving signal provided from a previous stage, a following gate line driving signal provided from a following stage, and an input voltage signal externally provided, and a pull-down driver to generate the second control signal to control the pull-down part in response to a third control signal provided from the pull-up driver and the input voltage signal, in which the second control signal swings between first and second voltage levels in association with the input voltage signal that swings between predetermined voltage levels.

Abstract: In a gate driving circuit and a display apparatus, the gate driving circuit comprises a plurality of stages. At least one of the stages comprises a pull-up section responsive to a first node signal; a pull-down section responsive to a second input signal; a discharging section discharging the first node signal in response to the second input signal; a first holding section responsive to the first clock signal, maintaining the first node signal at the off-voltage; and a second holding section responsive to the second clock signal, maintaining the first node signal at the off-voltage. The second holding section has a greater transistor width-to-length ratio than the first holding section. Therefore, an abnormal gate-on signal is less likely to occur, reducing driving defects of the display apparatus.

Abstract: A display substrate includes source lines, gate lines, an output pad part, a fan-out part and a first voltage line part. The source lines are in a display area. The gate lines cross the source lines. The output pad part is in a peripheral area surrounding the display area and is electrically connected to output terminals of a driving chip. The fan-out part is electrically connected between the output pad part and the source lines. The first voltage line part is inclined with respect to a central line of a chip area in which the driving chip is mounted toward opposite sides of the chip area to cross the fan-out part. Therefore, the line reactance of the fan-out part is decreased and the uniformity of the line resistance of the fan-out part is increased to improve image display quality.

Abstract: A display substrate includes an output pads section, a fan-out section, a first power wiring section and a first conductive pattern. The output pads section is electrically connected to a plurality of output terminals of a first driver chip. The fan-out section electrically connects the output pads section to a plurality of source wirings. The first power wiring section is extended along a longitudinal direction of a plurality of gate wirings that cross with source wirings of the display substrate. The first power wiring section propagates at least first and second power-delivering voltages to the driver chip. The first conductive pattern is insulatively overlapped with the first power wiring section in an intermediate area between the output pads sections of an adjacent second driver chip. The first conductive pattern thereby defines a capacitive shunting path for voltage transients or ripples.

Abstract: A shift register in which multiple stages are connected one after another to each other, the multiple stages having a first stage in which a start signal is coupled to an input terminal, the shift register sequentially outputting output signals of respective stages. The multiple stages have odd stages for receiving a first clock signal, and even stages for receiving a second clock signal having a phase opposite to the first clock signal. Each of the multiple stages has a pull-up section for providing a corresponding one of the first and second clock signals to an output terminal. A pull-up driving section is connected to an input node of the pull-up section. A pull-down section provides a first power voltage to the output terminal. A pull-down driving section is connected to an input node of the pull-down section.

Abstract: An inverter driving apparatus for driving a plurality of lamp units is provided. The inverter driving apparatus includes a plurality of inverter boards for generating driving signals for driving respective lamp units based on a control signal and a voltage signal. Each lamp unit includes at least one lamp, and the plurality of inverter boards are connected in series and include a first outer inverter board receiving the control signal and a second outer inverter board located opposite the first outer inverter board receiving the voltage signal. Each of the plurality of inverter boards transmits the control signal and/or the voltage signal to at least one of the plurality of inverter boards adjacent thereto.

Abstract: A shift register has multiple stages each of which includes a pull-up part to generate a current gate line driving signal having a first state in response to a first control signal and a clock signal, a pull-down part to generate the current gate line driving signal having a second state in response to a second control signal, a pull-up driver to generate the first control signal to control the pull-up part in response to a previous gate line driving signal provided from a previous stage, a following gate line driving signal provided from a following stage, and an input voltage signal externally provided, and a pull-down driver to generate the second control signal to control the pull-down part in response to a third control signal provided from the pull-up driver and the input voltage signal, in which the second control signal swings between first and second voltage levels in association with the input voltage signal that swings between predetermined voltage levels.