Patents by Inventor Seung-Il Bok

Seung-Il Bok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8993436
    Abstract: A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Whan Ko, Jong-Sam Kim, Hong-Jae Shin, Seung-Il Bok, Sae-Il Son, Woo-Jin Jang
  • Publication number: 20140308810
    Abstract: A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.
    Type: Application
    Filed: March 6, 2014
    Publication date: October 16, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Whan KO, Jong-Sam KIM, Hong-Jae SHIN, Seung-Il BOK, Sae-Il SON, Woo-Jin JANG
  • Patent number: 8518723
    Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chong-Kwang Chang, Hong-Jae Shin, Nae-In Lee, Kwang-Hyeon Baik, Seung-Il Bok, Hyo-Jeong Kim
  • Publication number: 20100136790
    Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 3, 2010
    Inventors: Chong-Kwang Chang, Hong-Jae Shin, Nae-In Lee, Kwang-Hyeon Baik, Seung-Il Bok, Hyo-Jeong Kim