Patents by Inventor Seung Jae Chung

Seung Jae Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210155913
    Abstract: The present invention is related to the field of protein engineering technology which increases the enzymatic activity and thermal stability of human hyaluronidase which is an enzyme that hydrolyzes hyaluronic acid; and more particularly to hyaluronidase PH20 variants or fragments thereof, which comprise one or more amino acid residue substitutions in the region corresponding to the alpha-helix region and its linker region in the amino acid sequence of wild-type PH20 of SEQ ID NO: 1 and in which one or more amino acid residues at the N-terminus and/or the C-terminus are selectively cleaved additionally.
    Type: Application
    Filed: July 25, 2019
    Publication date: May 27, 2021
    Inventors: Soon Jae PARK, Hye-Shin CHUNG, Seung Joo LEE, Sun-Ah YOU, Hyung-Nam SONG, Chang Woo LEE
  • Patent number: 9298650
    Abstract: Disclosed are a memory system, a semiconductor memory device and a method of operating the same. The memory system includes: a memory controller to output a command, address and data; and a semiconductor memory device to store at least one page data in each memory cell in response to the command, the address and the data, the memory controller to separately output first address used for determining the at least one page data from the data and second address used for determining a word line coupled to at least one memory cell.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: March 29, 2016
    Assignee: SK HYNIX INC.
    Inventors: Wan Ik Cho, Sang Kyu Lee, Myung Su Kim, Seung Jae Chung
  • Publication number: 20140337574
    Abstract: Disclosed are a memory system, a semiconductor memory device and a method of operating the same. The memory system includes: a memory controller to output a command, address and data; and a semiconductor memory device to store at least one page data in each memory cell in response to the command, the address and the data, the memory controller to separately output first address used for determining the at least one page data from the data and second address used for determining a word line coupled to at least one memory cell.
    Type: Application
    Filed: September 18, 2013
    Publication date: November 13, 2014
    Applicant: SK HYNIX INC
    Inventors: Wan Ik CHO, Sang Kyu LEE, Myung Su KIM, Seung Jae CHUNG
  • Patent number: 8504896
    Abstract: A method of operating a nonvolatile memory device including a memory cell array having first and second main cells for storing external input data, first spare cells for storing data for error correction code (ECC) processing on the data stored in the first and second main cells and second spare cells for storing data for ECC processing on the data stored in the first and second main cells which involves reading the data stored in the first spare cells, reading the data stored in the second main cells and the data stored in the second spare cells, and performing the ECC processing on the data read from the second main cells using the data read from the first spare cells and the data read from the second spare cells.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: August 6, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang Kyu Lee, Seung Jae Chung
  • Patent number: 8154919
    Abstract: A nonvolatile memory device includes a read margin critical value calculation unit configured to calculate a critical value of a read margin between a read voltage and a threshold voltage of a specific cell, an interference value calculation unit configured to calculate an interference value affecting the threshold voltage of the specific cell, a comparison unit configured to compare the critical value and the interference value and to output a result of the comparison, and a data selection unit configured to output either first data, read from the specific cell using a first read voltage, or second data, read from the specific cell using a second read voltage, based on the result outputted from the comparison unit.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang Kyu Lee, Seung Jae Chung
  • Patent number: 8014207
    Abstract: A nonvolatile memory device includes an encoder configured to perform a scramble operation on input data, a digital sum value (DSV) generator configured to generate a DSV indicating a difference between a number of data ‘0’ and a number of data ‘1’ in the input data encoded by the encoder, a main cell unit of a page of a memory cell array, wherein the main cell unit is configured to store the input data encoded by the encoder, a spare cell unit of the page, wherein the spare cell unit is configured to store the DSV generated by the DSV generator, and a read voltage setting unit configured to determine a read voltage for the page by comparing a DSV generated from the stored data of the main cell unit and the stored DSV of the spare cell unit.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 6, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Han Ryu, Joong Seob Yang, Seung Jae Chung
  • Publication number: 20100332946
    Abstract: A method of operating a nonvolatile memory device including a memory cell array having first and second main cells for storing external input data, first spare cells for storing data for error correction code (ECC) processing on the data stored in the first and second main cells and second spare cells for storing data for ECC processing on the data stored in the first and second main cells which involves reading the data stored in the first spare cells, reading the data stored in the second main cells and the data stored in the second spare cells, and performing the ECC processing on the data read from the second main cells using the data read from the first spare cells and the data read from the second spare cells.
    Type: Application
    Filed: May 5, 2010
    Publication date: December 30, 2010
    Inventors: Sang Kyu Lee, Seung Jae Chung
  • Publication number: 20100202196
    Abstract: A nonvolatile memory device includes a read margin critical value calculation unit configured to calculate a critical value of a read margin between a read voltage and a threshold voltage of a specific cell, an interference value calculation unit configured to calculate an interference value affecting the threshold voltage of the specific cell, a comparison unit configured to compare the critical value and the interference value and to output a result of the comparison, and a data selection unit configured to output either first data, read from the specific cell using a first read voltage, or second data, read from the specific cell using a second read voltage, based on the result outputted from the comparison unit.
    Type: Application
    Filed: December 28, 2009
    Publication date: August 12, 2010
    Inventors: Sang Kyu Lee, Seung Jae Chung
  • Publication number: 20100182830
    Abstract: A nonvolatile memory device includes an encoder configured to perform a scramble operation on input data, a digital sum value (DSV) generator configured to generate a DSV indicating a difference between a number of data ‘0’ and a number of data ‘1’ in the input data encoded by the encoder, a main cell unit of a page of a memory cell array, wherein the main cell unit is configured to store the input data encoded by the encoder, a spare cell unit of the page, wherein the spare cell unit is configured to store the DSV generated by the DSV generator, and a read voltage setting unit configured to determine a read voltage for the page by comparing a DSV generated from the stored data of the main cell unit and the stored DSV of the spare cell unit.
    Type: Application
    Filed: December 30, 2009
    Publication date: July 22, 2010
    Inventors: Seung Han RYU, Joong Seob Yang, Seung Jae Chung
  • Patent number: 7543218
    Abstract: A method of decoding DVD-format data may include: receiving a demodulated error correction code (ECC) block of DVD-format data; parity-of-inner-code-correcting (PI-correcting) the demodulated ECC block as needed; identifying any errant column within the PI-corrected block which merits PO-correction; and selectively PO-correcting only the errant PI-corrected columns to obtain a decoded version of ECC block.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: June 2, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-Jae Chung
  • Patent number: 7249300
    Abstract: Integrated circuit devices include a core block having a plurality of output ports and a plurality of input ports and a vector input terminal. The core block generates core internal data responsive to output data from the input ports and is configured to output the core internal data during scan testing and to selectively generate core output data for the output ports responsive to the core internal data or to test vector serial input data from the vector input terminal. An input side sub logic circuit unit generates sub data for the plurality of input ports responsive to data input to the first sub logic circuit unit. A multiplexer (MUX) unit between the core block and the first sub logic circuit unit selectively provides the sub data or the output data as inputs to the input ports of the core block responsive to a MUX control signal.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: July 24, 2007
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Seung-jae Chung, Yong-chun Kim
  • Patent number: 6950929
    Abstract: A data processing device having a central processing unit for fetching instructions from a program memory, decoding the instructions and sending a signal to a coprocessor if a coprocessor-type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal; and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieved from the loop buffer for execution in a subsequent iteration of the loop, and wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: September 27, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Jae Chung, Yong Chun Kim
  • Patent number: 6950922
    Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: September 27, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-jae Chung, Yong-chun Kim
  • Publication number: 20050193289
    Abstract: A method of decoding DVD-format data may include: receiving a demodulated error correction code (ECC) block of DVD-format data; parity-of-inner-code-correcting (PI-correcting) the demodulated ECC block as needed; identifying any errant column within the PI-corrected block which merits PO-correction; and selectively PO-correcting only the errant PI-corrected columns to obtain a decoded version of ECC block.
    Type: Application
    Filed: September 24, 2004
    Publication date: September 1, 2005
    Inventor: Seung-Jae Chung
  • Patent number: 6872115
    Abstract: One object of the present invention is to provide a blade for forming ribs that is able to improve wear resistance; in order to achieve the object, the present invention provide a blade for forming ribs that forms ribs either on the surface of a substrate or via an undercoating layer on the surface of a substrate by moving a blade body in a fixed direction relative to a paste film in the state in which comb teeth formed on at least a portion of the periphery of said blade body are penetrated into said paste film formed on the surface of said substrate to plasticly deform said paste film; wherein, the surface of said comb teeth formed on said blade body that makes contact with said paste film is coated with a compound layer in which hard particles are dispersed in a metal.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: March 29, 2005
    Assignees: Mitsubishi Material Corporation, Samsung SDI Co., Ltd.
    Inventors: Hideaki Sakurai, Kunio Sugamura, Yoshio Kanda, Ryuji Uesugi, Yoshirou Kuromitsu, Young Cheul Kang, Eun Gi Heo, Young Soo Seo, Seung Jae Chung, Joon Min Kim, Hyun Sub Lee
  • Publication number: 20040128598
    Abstract: Integrated circuit devices include a core block having a plurality of output ports and a plurality of input ports and a vector input terminal. The core block generates core internal data responsive to output data from the input ports. The core block is configured to output the core internal data during scan testing and to selectively generate core output data for the output ports responsive to the core internal data or to test vector serial input data from the vector input terminal. An input side sub logic circuit unit is configured for dynamic simulation testing and is coupled to the input ports of the core block. The input side sub logic circuit unit generates sub data for the plurality of input ports responsive to data input to the first sub logic circuit unit. A multiplexer (MUX) unit between the core block and the first sub logic circuit unit selectively provides the sub data or the output data as inputs to the input ports of the core block responsive to a MUX control signal.
    Type: Application
    Filed: October 29, 2003
    Publication date: July 1, 2004
    Inventors: Seung-Jae Chung, Yong-Chun Kim
  • Publication number: 20030212876
    Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.
    Type: Application
    Filed: March 13, 2003
    Publication date: November 13, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Chung, Yong-Chun Kim
  • Publication number: 20030056313
    Abstract: One object of the present invention is to provide a blade for forming ribs that is able to improve wear resistance; in order to achieve the object, the present invention provide a blade for forming ribs that forms ribs either on the surface of a substrate or via an undercoating layer on the surface of a substrate by moving a blade body in a fixed direction relative to a paste film in the state in which comb teeth formed on at least a portion of the periphery of said blade body are penetrated into said paste film formed on the surface of said substrate to plasticly deform said paste film; wherein, the surface of said comb teeth formed on said blade body that makes contact with said paste film is coated with a compound layer in which hard particles are dispersed in a metal.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 27, 2003
    Inventors: Hideaki Sakurai, Kunio Sugamura, Yoshio Kanda, Ryuji Uesugi, Yoshirou Kuromitsu, Young Cheul Kang, Eun Gi Heo, Young Soo Seo, Seung Jae Chung, Joon Min Kim, Hyun Sub Lee
  • Publication number: 20020178350
    Abstract: A data processing device comprising a central processing unit (CPU) for fetching instructions from a program memory, decoding the instructions and sending a signal (CCLK) to a coprocessor if a coprocessor type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal (CCLK); and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieve from the loop buffer for execution in a subsequent iteration of the loop, wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.
    Type: Application
    Filed: May 24, 2001
    Publication date: November 28, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seung Jae Chung, Yong Chun Kim
  • Publication number: 20020155937
    Abstract: One object of the present invention is to provide a paste that is easily coated, has a comparatively long aging time and is able to maintain the shape of the ribs following plastic deformation; in order to achieve the object, the present invention provides a paste comprising 50-95% by weight of glass powder or glass-ceramic mixed powder, 0.1-15% by weight of a resin, and 3-60% by weight of a plurality of kinds of solvents, wherein each boiling point of the plurality of kinds of solvents differs by 30° C. or more; and, the plurality of kinds of solvents contain one or more low boiling point solvents which are low boiling point solvents having a boiling point from 100° C. to 180° C., and one or more high boiling point solvents which are high boiling point solvents having a boiling point from 190° C. to 450° C.
    Type: Application
    Filed: January 4, 2002
    Publication date: October 24, 2002
    Inventors: Ryuji Uesugi, Ikiko Hashimoto, Yoshio Kanda, Yoshirou Kuromitsu, Young Cheul Kang, Seung Jae Chung, Joon Mim Kim, Kanzo Yoshikawa