Abstract: A deposition apparatus includes: a chamber; a support unit within the chamber and including a chuck and a driving member, wherein a substrate is seated on the chuck, wherein the chuck has a first process position and a second process position, wherein the first process position is for processing the substrate in a first process, wherein the second process position is for processing the substrate in a second process, wherein the driving member moves the chuck between the first process position and the second process position; a showerhead supplying process gas toward the substrate, when the chuck is located in the first process position; a power supply unit supplying power to generate plasma between the chuck and the showerhead; and a first ultraviolet lamp disposed in the chamber and emitting ultraviolet rays toward the substrate, when the chuck is located in the second process position.

Abstract: A method of manufacturing an integrated circuit device, the method including forming a doped silicon oxide film on a substrate by supplying, onto the substrate, a silicon precursor, an oxidant, and at least two dopant sources including dopant elements that are different from each other such that the doped silicon oxide film includes at least two dopant elements; forming a vertical hole in the doped silicon oxide film by dry-etching the doped silicon oxide film; and forming a vertical structure in the vertical hole, wherein the silicon precursor includes a monosilane compound, a disilane compound, a siloxane compound, or a combination thereof, and the silicon precursor includes a Si—H functional group, and a C1-C10 oxy group or a C1-C10 organoamino group.

Abstract: Disclosed are a three-dimensional semiconductor memory device, a method of fabricating the same, and an electronic system including the same. The semiconductor memory device may include a substrate including a first region and a second region, a plurality of stacks including first and second stacks, each of which includes interlayer insulating layers and gate electrodes stacked alternately with the interlayer insulating layers on the substrate and has a stepped structure on the second region, an insulating layer on stepped structure of the first stack, a plurality of vertical channel structures provided on the first region to penetrate the first stack, and a separation structure separating the first and second stacks from each other. The insulating layer may include one or more dopants, and a dopant concentration of the insulating layer may decrease as a distance from the substrate increases.

Abstract: A semiconductor device includes: a stepped connection portion having a plurality of conductive pad portions disposed on a substrate; an insulating block covering the plurality of conductive pad portions, wherein the insulating block has a first surface and a second surface, wherein the first surface faces the stepped connection portion, wherein the second surface is flat and extends in a direction parallel to a first surface of the substrate, wherein the insulating block includes a silicon oxide film doped with a dopant element including a metalloid element or a non-metal element, wherein the dopant element has an atomic weight within a range of 5 to 15; and at least one plug structure passing through the insulating block in a vertical direction with respect to the first surface of substrate.