Abstract: A display device is disclosed, and the display device includes a substrate including first to third display regions, the second and the third display regions being spaced from each other, each of the second and third display regions having an area smaller than that of the first display region and being continuous to the first display region, first to third pixels in the first to third display regions, first to third lines connected to the first to third pixels, and a dummy part configured to compensate for a difference between a load value of the first lines and load values of the second and third lines, wherein the second display region includes a first sub-region adjacent to the first display region and a second sub-region spaced from the first display region, and the third display region includes a third sub-region adjacent to the first display region and a fourth sub-region spaced from the first display region.

Abstract: A display device includes a substrate including a first pixel region, a second pixel region having an area smaller than that of the first pixel region, and a peripheral region surrounding the first pixel region and the second pixel region, a second pixel provided in the second pixel region, a second line connected to the second pixel, an extension line extended to the peripheral region, a dummy part located in the peripheral region to overlap with the extension line, a power line connected to the first and second pixel regions, and a connection line located in the peripheral region to be connected to the dummy part, the connection line being electrically connected to a portion of the second pixel region, wherein the second pixel region includes a first sub-pixel region connected to the connection line and a second sub-pixel region except the first sub-pixel region.

Abstract: The present disclosure relates to a display device including first pixels disposed in a first pixel area, and connected to first scan lines; second pixels disposed in a second pixel area, and connected to second scan lines; a timing controller configured to supply a first clock signal and a second clock signal to a first clock line and a second clock line, respectively; a first scan driver configured to receive the first clock signal through the first clock line, and to supply a first scan signal to the first scan lines; and a second scan driver configured to receive the second clock signal through the second clock line, and to supply a second scan signal to the second scan lines, wherein the second pixel area has a smaller width than the first pixel area.

Abstract: A display device is provided. The display device comprises a display panel including a plurality of signal pads and one or more dummy pads, and at least one flexible wiring board providing signals to the signal pads, wherein a maximum bias period of signals provided to a pair of adjacent signal pads with at least one dummy pad interposed therebetween is longer than a maximum bias period of signals provided to a pair of adjacent signal pads with no dummy pad disposed therebetween.

Abstract: A display device includes a substrate having a display area and a non-display area. A plurality of pixels is disposed in the display area of the substrate. A plurality of data lines is connected to the plurality of pixels. A crack sensing line is connected to at least one of the plurality of data lines. The crack sensing line is disposed in the non-display area of the substrate. A dummy pattern layer is connected to the crack sensing line.

Abstract: A display device is provided. The display device comprises a display panel including a plurality of signal pads and one or more dummy pads, and at least one flexible wiring board providing signals to the signal pads, wherein a maximum bias period of signals provided to a pair of adjacent signal pads with at least one dummy pad interposed therebetween is longer than a maximum bias period of signals provided to a pair of adjacent signal pads with no dummy pad disposed therebetween.

Abstract: A stage including: an output circuit connected to a first node and a second node; an input connected to a third node and a fourth node; and a plurality of signal processors between the output and the input, the plurality of signal processors electrically connecting the first node and the third node and electrically connecting the second node and the fourth node, wherein the input includes: a seventh transistor connected between a first input terminal and the fourth node and having a gate electrode connected to a second input terminal; a plurality of eighth transistors serially connected between the third node and the second input terminal and having gate electrodes connected to the fourth node; and a ninth transistor connected between the third node and a second power source and having a gate electrode connected to the second input terminal.

Abstract: A pixel includes an organic light emitting diode (OLED), a pixel circuit, and first and second transistors. The OLD includes a cathode electrode connected to a second power source. The pixel circuit includes a driving transistor having a gate electrode initialized by a third power source. The driving transistor controls the amount of current flowing from a first power source to the second power source via the OLED. The first transistor is connected between a fourth power source and the second power source and an anode electrode of the OLED. The first transistor is turned on based on a scan signal is supplied to a scan line. The second transistor is connected between a data line and the pixel circuit. The second transistor is turned on when the scan signal is supplied to the ith scan line.

Abstract: A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines.

Abstract: An organic light-emitting display device includes: a substrate on which a display area and a non-display area surrounding the display area are defined, the display area includes a main area and at least one protruding area, and a plurality of pixels is in the display area; a first signal line on the substrate in the main area to provide signals to the plurality of pixels; a second signal line on the substrate in the protruding area to provide signals to the plurality of pixels; a compensation line on the substrate in the non-display area and electrically connected to the second signal line; and a bridge pattern over the second signal line and the compensation line in the non-display area and electrically connecting the second signal line with the compensation line, the bridge pattern including a double-bridge structure.

Abstract: A display device includes: a first pixel including a first organic light emitting diode; an initialization voltage generator for generating a first initialization voltage to be supplied to an anode of the first organic light emitting diode; and a timing controller including a first lookup table in which a plurality of first initialization voltage values corresponding to a plurality of maximum luminances are recorded, the timing controller being configured to determine a value of the first initialization voltage, based on reception information on a target maximum luminance and the first lookup table.

Abstract: A stage including: an output circuit connected to a first node and a second node; an input connected to a third node and a fourth node; and a plurality of signal processors between the output and the input, the plurality of signal processors electrically connecting the first node and the third node and electrically connecting the second node and the fourth node, wherein the input includes: a seventh transistor connected between a first input terminal and the fourth node and having a gate electrode connected to a second input terminal; a plurality of eighth transistors serially connected between the third node and the second input terminal and having gate electrodes connected to the fourth node; and a ninth transistor connected between the third node and a second power source and having a gate electrode connected to the second input terminal.

Abstract: A pixel includes an organic light emitting diode (OLED), a pixel circuit, and first and second transistors. The OLD includes a cathode electrode connected to a second power source. The pixel circuit includes a driving transistor having a gate electrode initialized by a third power source. The driving transistor controls the amount of current flowing from a first power source to the second power source via the OLED. The first transistor is connected between a fourth power source and the second power source and an anode electrode of the OLED. The first transistor is turned on based on a scan signal is supplied to a scan line. The second transistor is connected between a data line and the pixel circuit. The second transistor is turned on when the scan signal is supplied to the ith scan line.

Abstract: An organic light-emitting display device includes: a substrate on which a display area and a non-display area surrounding the display area are defined, the display area includes a main area and at least one protruding area, and a plurality of pixels is in the display area; a first signal line on the substrate in the main area to provide signals to the plurality of pixels; a second signal line on the substrate in the protruding area to provide signals to the plurality of pixels; a compensation line on the substrate in the non-display area and electrically connected to the second signal line; and a bridge pattern over the second signal line and the compensation line in the non-display area and electrically connecting the second signal line with the compensation line, the bridge pattern including a double-bridge structure.

Abstract: A display device includes: a first pixel including a first organic light emitting diode; an initialization voltage generator for generating a first initialization voltage to be supplied to an anode of the first organic light emitting diode; and a timing controller including a first lookup table in which a plurality of first initialization voltage values corresponding to a plurality of maximum luminances are recorded, the timing controller being configured to determine a value of the first initialization voltage, based on reception information on a target maximum luminance and the first lookup table.

Abstract: A display device includes: a first pixel including a first organic light emitting diode; an initialization voltage generator for generating a first initialization voltage to be supplied to an anode of the first organic light emitting diode; and a timing controller including a first lookup table in which a plurality of first initialization voltage values corresponding to a plurality of maximum luminances are recorded, the timing controller being configured to determine a value of the first initialization voltage, based on reception information on a target maximum luminance and the first lookup table.

Abstract: The present disclosure relates to a display device including first pixels disposed in a first pixel area, and connected to first scan lines; second pixels disposed in a second pixel area, and connected to second scan lines; a timing controller configured to supply a first clock signal and a second clock signal to a first clock line and a second clock line, respectively; a first scan driver configured to receive the first clock signal through the first clock line, and to supply a first scan signal to the first scan lines; and a second scan driver configured to receive the second clock signal through the second clock line, and to supply a second scan signal to the second scan lines, wherein the second pixel area has a smaller width than the first pixel area.

Abstract: A display device includes a substrate having a pixel area with at least a first rounded corner portion and first to third non-pixel areas arranged sequentially along an outer circumference of the pixel area. An internal circuit in the first non-pixel area has a first end portion adjacent to the first rounded corner portion of the pixel area. The first end portion of the internal circuit is rounded in accordance with the first rounded corner portion. A plurality of routing wires are in the third non-pixel area below the pixel area. The routing wires extending to the pixel area via the second non-pixel area and the first non-pixel area. The routing wires include at least a first routing wire connected to the pixel area passing an area of the first end portion of the internal circuit.

Abstract: A display device including a first pixel area including first pixels, a second pixel area including second pixels, a third pixel area including third pixels, and a display driver configured to control image display operations of the first pixel area, the second pixel area, and the third pixel area according to a first mode or a second mode, wherein the first pixel area includes a first sub-pixel area, and a second sub-pixel area between the first sub-pixel area and the second pixel area, and wherein the first sub-pixel area is configured to display a black image in the first mode, and the second sub-pixel area is configured to display a dummy image.

Abstract: A display device includes: a first pixel including a first organic light emitting diode; an initialization voltage generator for generating a first initialization voltage to be supplied to an anode of the first organic light emitting diode; and a timing controller including a first lookup table in which a plurality of first initialization voltage values corresponding to a plurality of maximum luminances are recorded, the timing controller being configured to determine a value of the first initialization voltage, based on reception information on a target maximum luminance and the first lookup table.