Abstract: A stage includes an output, an input, signal processors, and a stabilizer. The output supplies a voltage of a first or second power source to an output terminal based on voltages of first and second nodes. The input controls voltages of third and fourth nodes based on signals to a first and second input terminals. A first signal processor controls the voltage of the first node based on the voltage of the second node. A second signal processor is connected to a fifth node and controls the voltage of the first node based on a signal to a third input terminal. A third signal processor controls the voltage of the fourth node based on the voltage of the third node and the signal to the third input terminal. The stabilizer is connected between the second signal processor and input to control voltage drop widths of the third and fourth nodes.

Abstract: A display device includes first pixels in a first pixel region and connected to first scan lines and second pixels in a second pixel region connected to second scan lines. The second pixel has a width less than the first pixel region. The display device also includes a first scan driver to supply first scan signals to the first scan lines, a second scan driver to supply second scan signals to the second scan lines, a first signal line to supply a first driving signal to the first scan driver and the second scan driver, and a signal delay circuit connected to the first signal line to delay the first driving signal.

Abstract: The present disclosure relates to a display device including first pixels disposed in a first pixel area, and connected to first scan lines; second pixels disposed in a second pixel area, and connected to second scan lines; a timing controller configured to supply a first clock signal and a second clock signal to a first clock line and a second clock line, respectively; a first scan driver configured to receive the first clock signal through the first clock line, and to supply a first scan signal to the first scan lines; and a second scan driver configured to receive the second clock signal through the second clock line, and to supply a second scan signal to the second scan lines, wherein the second pixel area has a smaller width than the first pixel area.

Abstract: A display device includes a first pixel region and a second pixel region having different widths. First pixels in the first pixel region each include a first transistor. Second pixels in the second pixel region each include a second transistor performing a same function as the first transistor. At least one of a channel width and a channel length of the first transistor of the first and second pixels is be different from one another.

Abstract: A display device includes a substrate, first pixels, second pixels, and third pixels. The substrate has a first pixel area, a second pixel area, and a third pixel area. The first pixels are in the first pixel area and are connected to first scan lines and first emission control lines. The second pixels are in the second pixel area and are connected to second scan lines and second emission control lines. The third pixels are in the third pixel area and are connected to third scan lines and third emission control lines. The second scan lines are spaced apart from the third scan lines, and the second emission control lines are spaced apart from the third emission control lines.

Abstract: A display device includes a substrate having a pixel area with at least a first rounded corner portion and first to third non-pixel areas arranged sequentially along an outer circumference of the pixel area. An internal circuit in the first non-pixel area has a first end portion adjacent to the first rounded corner portion of the pixel area. The first end portion of the internal circuit is rounded in accordance with the first rounded corner portion. A plurality of routing wires are in the third non-pixel area below the pixel area. The routing wires extending to the pixel area via the second non-pixel area and the first non-pixel area. The routing wires include at least a first routing wire connected to the pixel area passing an area of the first end portion of the internal circuit.

Abstract: A display device includes a display panel including a plurality of scan lines, a plurality of data lines, and a plurality of unit pixels. Each unit pixel includes a plurality of sub-pixels, each coupled to a respective data line. The plurality of sub-pixels includes a red sub-pixel, a first green sub-pixel, a blue sub-pixel, and a second green sub-pixel. The display device further includes a data driver configured to output data signals via output channels. The display device additionally includes a plurality of demultiplexers configured to selectively connect data signals output from the output channels to the plurality of sub-pixels in response to a plurality of select signals that are sequentially provided to the plurality of demultiplexers. The display device further includes a scan driver configured to provide scan signals to the unit pixels through the scan lines, and a timing controller.

Abstract: A display device includes a substrate including a first pixel area, a second pixel area, and a third pixel area, each of the second and third pixel areas having a smaller surface area than the first pixel area and being connected to the first pixel area, first to third pixels provided in the first to third pixel areas, respectively, first to third lines connected to the first to third pixels, respectively, a line connecting part connecting the second and third lines, and a dummy unit overlapping the line connecting part to compensate for a difference of a load value of the first line and a load value of the second line.

Abstract: An emission driver includes light emission control drivers electrically connected to light emission control lines, the light emission control drivers including an (n?1)th light emission control driver configured to provide an (n?1)th carry signal, n being an integer greater than or equal to 2, and an (n)th light emission control driver adjacent to the (n?1)th light emission control driver, the (n)th light emission control drive being configured to generate an (n)th light emission control signal for controlling a light emission time of a pixel based on the (n?1)th carry signal, and to generate an (n)th carry signal based on the (n)th light emission control signal.