Abstract: A display device according to an embodiment includes: a substrate; a transistor that is disposed on the substrate; a light emitting diode that is disposed on the substrate, and connected to the transistor; and a passivation layer that is disposed between the transistor and the light emitting diode, wherein a surface step of the passivation layer is within a range of and including 1 nm to 30 nm.

Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.

Abstract: A semiconductor device includes a substrate, a thermal conduction layer on the substrate, a first wire pattern on the thermal conduction layer, a first semiconductor pattern a second semiconductor pattern, and a gate electrode between the first semiconductor pattern and the second semiconductor pattern. The gate electrode surrounds a periphery of the first wire pattern. A concentration of impurity of the thermal conduction layer is different from that of the substrate. The first wire pattern includes a first end and a second end. The concentration of impurity contained in the first wire pattern is higher than that contained in the thermal conduction layer and that contained in the substrate. The first semiconductor pattern is in contact with the first end of the first wire pattern and the thermal conduction layer. The second semiconductor pattern is in contact with the second end of the first wire pattern.

Abstract: A semiconductor device includes a first fin pattern, which includes a first lower pattern and a first upper pattern stacked sequentially on a substrate, the first upper pattern including a first part and second parts respectively disposed on both sides of the first part, a gate electrode, which is formed on the first part to intersect the first fin pattern, and source/drain regions, which are formed on the second parts, respectively. A dopant concentration of the first upper pattern is higher than a dopant concentration of the first lower pattern and a dopant concentration of the substrate, and the dopant concentration of the first lower pattern is different from the dopant concentration of the substrate.

Abstract: There is provided a semiconductor device capable of suppressing generation of leakage current of a diode, by applying a voltage to a gate of a gated junction diode (GJD). The semiconductor device includes an internal circuit connected with an input-output terminal, and an electrostatic discharge (ESD) protection circuit configured to protect the internal circuit from ESD, the ESD protection circuit including a first diode, wherein the first diode includes a first gate which is formed on a substrate and to which a first recovery voltage is applied, a first well of a first conductivity type which is formed within the substrate and under the first gate, a first impurity region of the first conductivity type which is formed on one side of the first gate and within the first well and is higher in doping concentration than that of the first well, and a second impurity region of a second conductivity type which is formed on other side of the first gate and within the first well.

Abstract: A semiconductor device includes a substrate, a thermal conduction layer on the substrate, a first wire pattern on the thermal conduction layer, a first semiconductor pattern a second semiconductor pattern, and a gate electrode between the first semiconductor pattern and the second semiconductor pattern. The gate electrode surrounds a periphery of the first wire pattern. A concentration of impurity of the thermal conduction layer is different from that of the substrate. The first wire pattern includes a first end and a second end. The concentration of impurity contained in the first wire pattern is higher than that contained in the thermal conduction layer and that contained in the substrate. The first semiconductor pattern is in contact with the first end of the first wire pattern and the thermal conduction layer. The second semiconductor pattern is in contact with the second end of the first wire pattern.

Abstract: A semiconductor device includes a first fin pattern, which includes a first lower pattern and a first upper pattern stacked sequentially on a substrate, the first upper pattern including a first part and second parts respectively disposed on both sides of the first part, a gate electrode, which is formed on the first part to intersect the first fin pattern, and source/drain regions, which are formed on the second parts, respectively. A dopant concentration of the first upper pattern is higher than a dopant concentration of the first lower pattern and a dopant concentration of the substrate, and the dopant concentration of the first lower pattern is different from the dopant concentration of the substrate.