Patents by Inventor Seung-Jin MUN
Seung-Jin MUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10622256Abstract: A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.Type: GrantFiled: March 28, 2016Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jin Mun, Dong-Hoon Khang, Woo-Ram Kim, Cheol Kim, Dong-Seok Lee, Yong-Joon Choi, Seung-Mo Ha, Do-Hyoung Kim
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Patent number: 9985025Abstract: An active pattern structure may include a substrate including an active pattern array defined by a plurality of trenches including first to third trenches, and first to third isolation patterns in the first to third trenches, respectively. The active pattern array may include a plurality of first and second active patterns extending in a first direction, and the first to third trenches may be between the first and second active patterns and may include different widths from each other. The active pattern array may include an active pattern group including one of the first active patterns and one of the second active patterns sequentially arranged in a second direction substantially perpendicular to the first direction. Each of the first and second active patterns may have a minute width.Type: GrantFiled: April 25, 2017Date of Patent: May 29, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Il Kim, Seung-Jin Mun, Kwang-Yong Yang, Young-Mook Oh, Ah-Young Cheon, Seung-Mo Ha
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Publication number: 20180145072Abstract: An active pattern structure may include a substrate including an active pattern array defined by a plurality of trenches including first to third trenches, and first to third isolation patterns in the first to third trenches, respectively. The active pattern array may include a plurality of first and second active patterns extending in a first direction, and the first to third trenches may be between the first and second active patterns and may include different widths from each other. The active pattern array may include an active pattern group including one of the first active patterns and one of the second active patterns sequentially arranged in a second direction substantially perpendicular to the first direction. Each of the first and second active patterns may have a minute width.Type: ApplicationFiled: April 25, 2017Publication date: May 24, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Ki-Il KIM, Seung-Jin MUN, Kwang-Yong YANG, Young-Mook OH, Ah-Young CHEON, Seung-Mo HA
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Patent number: 9972538Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.Type: GrantFiled: June 29, 2016Date of Patent: May 15, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Cheol Kim, Dong-Hoon Khang, Do-Hyoung Kim, Seung-Jin Mun, Yong-Joon Choi, Seung-Mo Ha
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Patent number: 9966375Abstract: A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.Type: GrantFiled: February 22, 2016Date of Patent: May 8, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Joon Choi, Tae-Yong Kwon, Mirco Cantoro, Chang-Jae Yang, Dong-Hoon Khang, Woo-Ram Kim, Cheol Kim, Seung-Jin Mun, Seung-Mo Ha, Do-Hyoung Kim, Seong-Ju Kim, So-Ra You, Woong-ki Hong
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Publication number: 20170040221Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.Type: ApplicationFiled: June 29, 2016Publication date: February 9, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Cheol KIM, Dong-Hoon KHANG, Do-Hyoung KIM, Seung-Jin MUN, Yong-Joon CHOI, Seung-Mo HA
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Publication number: 20160315085Abstract: A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.Type: ApplicationFiled: February 22, 2016Publication date: October 27, 2016Inventors: Yong-Joon CHOI, Tae-Yong KWON, Mirco CANTORO, Chang-Jae YANG, Dong-Hoon KHANG, Woo-Ram KIM, Cheol KIM, Seung-Jin MUN, Seung-Mo HA, Do-Hyoung KIM, Seong-Ju KIM, So-Ra YOU, Woong-ki HONG
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Publication number: 20160307803Abstract: A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.Type: ApplicationFiled: March 28, 2016Publication date: October 20, 2016Inventors: Seung-Jin MUN, Dong-Hoon KHANG, Woo-Ram KIM, Cheol KIM, Dong-Seok LEE, Yong-Joon CHOI, Seung-Mo HA, Do-Hyoung KIM