Patents by Inventor Seung Jong Yoo

Seung Jong Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7105455
    Abstract: A method of fabricating a nonvolatile memory device is disclosed. First, a lower insulating layer and a sacrificial layer are formed in sequence on a substrate. Then, a sacrificial layer pattern is formed through removing some part of the sacrificial layer by an etching process to expose some part of the lower insulating layer. At the same time, spacers are formed on sidewalls of the sacrificial layer pattern. The spacers are formed of polymers resulting from the etching of the sacrificial layer. The exposed lower insulating layer is removed to form a lower insulating layer pattern. Next, the sacrificial layer pattern and the spacers are removed. Accordingly, linewidth of a tunnel window which defined by the insulating layer pattern becomes narrow.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: September 12, 2006
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Seung Jong Yoo
  • Patent number: 7037826
    Abstract: A method of forming a bonding pad of a semiconductor device is disclosed. An example method forms a first insulating layer over a semiconductor substrate, forms a trench by removing some part of the first insulating layer, forms a top metal interconnect in the trench, forms a second insulating layer over the substrate including the top metal interconnect, and forms a contact hole by removing some part of the second insulating layer, the contact hole exposing a portion of the top metal interconnect. In addition, the example method forms a metal layer on the surface of the second insulating layer and the sidewalls and bottom of the contact hole, forms a metal pad by removing some parts of the metal layer, forms a third insulating layer over the second insulating layer and the metal pad, and exposes the metal pad on the second insulating layer by removing some part of the third insulating layer.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: May 2, 2006
    Assignee: DongbuAnam Semiconductor, Inc.
    Inventor: Seung Jong Yoo
  • Patent number: 6873292
    Abstract: A surface mounted type chip antenna comprises: a body including an upper surface, a lower surface, and four side surfaces; a feeding pad formed on the lower surface and the first side surface of the body; a radiation electrode formed on the upper surface of the body and electrically connected to the feeding pad; a short bar formed on the third side surface being opposite to the first side surface and connected to the radiation electrode; and a ground electrode formed on the lower surface of the body, spaced apart from the feeding pad, and connected to the short bar. When the antenna is installed in a mobile communication apparatus, a location where a maximum current is generated is remote from circuitry of the PCB of the mobile apparatus.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: March 29, 2005
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Jong Yoo, Jae Suk Sung
  • Publication number: 20040157395
    Abstract: A method of fabricating a nonvolatile memory device is disclosed. First, a lower insulating layer and a sacrificial layer are formed in sequence on a substrate. Then, a sacrificial layer pattern is formed through removing some part of the sacrificial layer by an etching process to expose some part of the lower insulating layer. At the same time, spacers are formed on sidewalls of the sacrificial layer pattern. The spacers are formed of polymers resulting from the etching of the sacrificial layer. The exposed lower insulating layer is removed to form a lower insulating layer pattern. Next, the sacrificial layer pattern and the spacers are removed. Accordingly, linewidth of a tunnel window which defined by the insulating layer pattern becomes narrow.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 12, 2004
    Inventor: Seung Jong Yoo
  • Publication number: 20040142549
    Abstract: A method of forming a bonding pad of a semiconductor device is disclosed. An example method forms a first insulating layer over a semiconductor substrate, forms a trench by removing some part of the first insulating layer, forms a top metal interconnect in the trench, forms a second insulating layer over the substrate including the top metal interconnect, and forms a contact hole by removing some part of the second insulating layer, the contact hole exposing a portion of the top metal interconnect. In addition, the example method forms a metal layer on the surface of the second insulating layer and the sidewalls and bottom of the contact hole, forms a metal pad by removing some parts of the metal layer, forms a third insulating layer over the second insulating layer and the metal pad, and exposes the metal pad on the second insulating layer by removing some part of the third insulating layer.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 22, 2004
    Inventor: Seung Jong Yoo
  • Publication number: 20030218573
    Abstract: Disclosed is a surface mounted type chip antenna in which a current path is linearly formed by forming a feeding pad and a short bar to be opposed to each other, and when the surface mounted type chip antenna is installed on a mobile communication apparatus, a location of generating maximum current is remote from circuits of the printed circuit board (PCB) of the mobile communication apparatus, and a mobile communication apparatus using the surface mounted type chip antenna.
    Type: Application
    Filed: December 26, 2002
    Publication date: November 27, 2003
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Jong Yoo, Jae Suk Sung
  • Publication number: 20030007390
    Abstract: A data output circuit for a memory device is disclosed. By decoding plural data signals and by operating output transistors coupled to different driving voltages and having a single output terminal, the interface with an outside circuit is performed through the single output terminal. The output terminal outputs output signals having voltage levels different from each other. Thus, the number of interface terminals, the instant consumption of current, the area of a pad, and the area of a chip are reduced.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 9, 2003
    Inventors: Hyun-woo Lee, Seung-jong Yoo