Patents by Inventor Seung Joo Baek

Seung Joo Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140623
    Abstract: A launch pad system includes a fuel vent port provided in a launch vehicle, a launch pad fuel tank provided outside the launch vehicle to store fuel, a fuel recovery line connecting the fuel vent port and the launch pad fuel tank such that the fuel is transferred therethrough, and a fuel transfer unit provided on the fuel recovery line to transfer the fuel, wherein the fuel may be recovered from the launch vehicle to the launch pad fuel tank.
    Type: Application
    Filed: July 11, 2023
    Publication date: May 2, 2024
    Applicant: KOREA AEROSPACE RESEARCH INSTITUTE
    Inventors: Kwang Kun PARK, I Sang YU, Seung Whan BAEK, Young Suk JUNG, Kie Joo CHO
  • Patent number: 9142678
    Abstract: In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: September 22, 2015
    Assignee: SK HYNIX INC.
    Inventor: Seung Joo Baek
  • Publication number: 20140299942
    Abstract: In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistorfrom being generated by the wall oxide film.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 9, 2014
    Inventor: Seung Joo BAEK
  • Patent number: 8853018
    Abstract: A method for manufacturing a semiconductor device having multi-channels is provided. The method includes etching an active region of a gate region and a device isolation layer of the gate to form a gate recess, forming a first gate buried in a lower portion of the gate recess, forming an active bridge on the first gate for connecting portions of the active region at both sides of the first gate, and forming a second gate on the first gate to cover the active bridge. Therefore, a multi-channel region can be formed.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 7, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seung Joo Baek
  • Patent number: 8772110
    Abstract: In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 8, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seung Joo Baek
  • Publication number: 20130320460
    Abstract: In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film.
    Type: Application
    Filed: December 20, 2012
    Publication date: December 5, 2013
    Applicant: SK HYNIX INC.
    Inventor: Seung Joo BAEK
  • Publication number: 20130309825
    Abstract: A method for manufacturing a semiconductor device having multi-channels is provided. The method includes etching an active region of a gate region and a device isolation layer of the gate to form a gate recess, forming a first gate buried in a lower portion of the gate recess, forming an active bridge on the first gate for connecting portions of the active region at both sides of the first gate, and forming a second gate on the first gate to cover the active bridge. Therefore, a multi-channel region can be formed.
    Type: Application
    Filed: December 20, 2012
    Publication date: November 21, 2013
    Applicant: SK HYNIX INC.
    Inventor: Seung Joo BAEK
  • Patent number: 8361864
    Abstract: A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: January 29, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Joo Baek
  • Patent number: 8106450
    Abstract: A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: January 31, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Joo Baek
  • Publication number: 20110306178
    Abstract: A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 15, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Seung Joo BAEK
  • Patent number: 7871887
    Abstract: A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: January 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung Do Kim, Seung Joo Baek
  • Patent number: 7803689
    Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: September 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Joo Baek
  • Publication number: 20100219470
    Abstract: A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 2, 2010
    Inventor: Seung Joo BAEK
  • Publication number: 20100041208
    Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area.
    Type: Application
    Filed: October 26, 2009
    Publication date: February 18, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Seung Joo BAEK
  • Patent number: 7608878
    Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 27, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Joo Baek
  • Publication number: 20090256194
    Abstract: A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 15, 2009
    Inventors: Kyung Do KIM, Seung Joo BAEK
  • Patent number: 7537986
    Abstract: A semiconductor device comprises an active region formed in a semiconductor substrate; a recess region being formed within the active region and defining a protruding portion; and a gate structure formed within the recess region.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: May 26, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Joo Baek
  • Publication number: 20080023754
    Abstract: A semiconductor device and a method for manufacturing the same includes forming a trench for forming a fin-type active region to have a wave shape to not connect a gate to an active region, thereby improving the speed of current flowing in the gate and reduce leakage current in a storage electrode. Additionally, the active region is expanded toward the length-wise direction to secure a sufficient storage node contact.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 31, 2008
    Inventor: Seung Joo Baek
  • Publication number: 20080003774
    Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area.
    Type: Application
    Filed: December 29, 2006
    Publication date: January 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Seung Joo Baek