Patents by Inventor Seung Joon Jeon

Seung Joon Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130009154
    Abstract: An array substrate for an organic electroluminescent display device includes a substrate including a display area and a non-display area; a gate line and a data line; a thin film transistor including a semiconductor layer of polycrystalline silicon, a gate insulating layer, a gate electrode, an inter insulating layer, a source electrode, and a drain electrode; auxiliary lines formed of a same material and on a same layer as the data line; a passivation layer of organic insulating material and including a drain contact hole exposing the drain electrode, and an auxiliary line contact hole exposing one of the auxiliary lines; and a first electrode and a line connection pattern on the passivation layer, wherein the first electrode contacts the drain electrode and the line connection pattern contacts the one of the first auxiliary pattern.
    Type: Application
    Filed: December 28, 2011
    Publication date: January 10, 2013
    Inventors: Hee-Dong CHOI, Seung-Joon JEON
  • Publication number: 20120302024
    Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 29, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Young-Ho LEE, Seung-Joon JEON, Tae-Hang AHN
  • Publication number: 20120302047
    Abstract: A method for fabricating a semiconductor device includes forming a structure having first surfaces at a height above a second surface, which is provided between the first surfaces, forming a first silicon layer on the structure, performing a tilt ion implantation process on the first silicon layer to form a crystalline region and an amorphous region, forming a second silicon layer on the amorphous region, removing the second silicon layer and the first silicon layer until a part of the second surface is exposed, thereby forming an etch barrier, and etching using the etch barrier to form an open part that exposes a part of a sidewall of the structure.
    Type: Application
    Filed: September 13, 2011
    Publication date: November 29, 2012
    Inventors: Mi-Ri LEE, Jae-Geun Oh, Seung-Joon Jeon, Jin-Ku Lee, Bong-Seok Jeon
  • Patent number: 8253204
    Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: August 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Ho Lee, Seung-Joon Jeon, Tae-Hang Ahn
  • Publication number: 20120104399
    Abstract: A method of fabricating an array substrate for an organic electroluminescent display device includes forming a semiconductor layer, a semiconductor dummy pattern, a first storage electrode and a first gate insulating layer on a substrate; forming a second gate insulating layer on the semiconductor layer and the first storage electrode; forming a gate electrode and a second storage electrode on the second gate insulating layer; forming ohmic contact layers by doping impurities into both sides of the semiconductor layer; forming an inter insulating layer on the gate electrode and the second storage electrode; forming source and drain electrodes and a third storage electrode on the inter insulating layer; forming a passivation layer on the source and drain electrodes and the third storage electrode; forming a first electrode and a fourth storage electrode on the passivation layer; and forming a spacer and a bank on the first electrode.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 3, 2012
    Inventors: Hee-Dong CHOI, Jin-Chae Jeon, Seung-Joon Jeon, Hoe-Yong Kim
  • Publication number: 20120007258
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.
    Type: Application
    Filed: November 4, 2010
    Publication date: January 12, 2012
    Inventors: Jae-Geun Oh, Seung-Joon Jeon, Jin-Ku Lee, Mi-Ri Lee, Bong-Seok Jeon
  • Publication number: 20100261355
    Abstract: A method for forming a high quality insulation layer on a semiconductor device is presented. The method includes a first step of supplying any one of a silicon source gas and an oxygen source gas into a process chamber in which a semiconductor substrate is placed; a second step of simultaneously supplying the silicon source gas and the oxygen source gas into the process chamber having undergone the first step and depositing a silicon oxide layer on the semiconductor substrate; and a third step of supplying any one of the silicon source gas and the oxygen source gas into the process chamber having undergone the second step.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 14, 2010
    Inventors: Sang Tae AHN, Ja Chun KU, Seung Joon JEON
  • Publication number: 20090261349
    Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
    Type: Application
    Filed: December 23, 2008
    Publication date: October 22, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Young-Ho LEE, Seung-Joon JEON, Tae-Hang AHN
  • Patent number: 7311860
    Abstract: The present invention relates to 1,3,5-tricyano-2,4,6-tris(vinyl)benzene derivatives and method for preparing the same. The 1,3,5-tricyano-2,4,6-tris(vinyl)benzene derivatives can be prepared by refluxing 1,3,5-tricyanomesitylene with N-formylamine dimethylacetal or substituted benzaldehyde, or by the Wittig reaction of 1,3,5-tricyano-2,4,6-tris[(diethoxyphosphoryl)methyl]benzene with substituted benzaldehyde. The 1,3,5-tricyano-2,4,6-tris(vinyl)benzene derivatives exhibit large first hyperpolarizability in solution and significant second harmonic generation (SHG) in the powder state, and are useful as optical devices such as electro-optic modulators, optical switch, or the like for treating optical signal in optical communication industry.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: December 25, 2007
    Assignee: Korea University Foundation
    Inventors: Bong-Rae Cho, Seung-Joon Jeon, Min-Haeng Cho
  • Publication number: 20040251452
    Abstract: The present invention relates to 1,3,5-tricyano-2,4,6-tris(vinyl)benzene derivatives and method for preparing the same. The 1,3,5-tricyano-2,4,6-tris(vinyl)benzene derivatives can be prepared by refluxing 1,3,5-tricyanomesitylene with N-formylamine dimethylacetal or substituted benzaldehyde, or by the Wittig reaction of 1,3,5-tricyano-2,4,6-tris[(diethoxyphosphoryl)methyl]benzene with substituted benzaldehyde. The 1,3,5-tricyano-2,4,6-tris(vinyl)benzene derivatives exhibit large first hyperpolarizability in solution and significant second harmonic generation (SHG) in the powder state, and are useful as optical devices such as electro-optic modulators, optical switch, or the like for treating optical signal in optical communication industry.
    Type: Application
    Filed: January 26, 2004
    Publication date: December 16, 2004
    Inventors: Bong-Rae Cho, Seung-Joon Jeon, Min-Haeng Cho
  • Patent number: 6479364
    Abstract: A method for forming a capacitor for a semiconductor device is provided. In the method, a storage electrode is formed of a polysilicon layer, and a hemispherical silicate glass (HSG) layer is optionally formed on the surface of the storage electrode to increase the surface area of the storage electrode. Next, a TaSiN layer as a diffusion barrier is formed, a TaON layer as a dielectric layer is formed, and then a TaSiN layer is formed on the TaON layer. Next, a plate electrode is formed on the TaSiN layer, thereby completing a capacitor. Diffusion of oxygen between the electrodes and the dielectric layer is effectively blocked, so that reduction of capacitance and occurrence of leakage current are prevented. Due to improved dielectric characteristics of the TaON layer, increasing the surface area of the dielectric layer—for example, by forming a HSG layer—may not be required, thereby increasing a processing margin between adjacent capacitors.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: November 12, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Dong Woo Shin, Seung Joon Jeon
  • Publication number: 20010036708
    Abstract: A method for forming a capacitor for a semiconductor device is provided. In the method, a storage electrode is formed of a polysilicon layer, and a hemispherical silicate glass (HSG) layer is optionally formed on the surface of the storage electrode to increase the surface area of the storage electrode. Next, a TaSiN layer as a diffusion barrier is formed, a TaON layer as a dielectric layer is formed, and then a TaSiN layer is formed on the TaON layer. Next, a plate electrode is formed on the TaSiN layer, thereby completing a capacitor. Diffusion of oxygen between the electrodes and the dielectric layer is effectively blocked, so that reduction of capacitance and occurrence of leakage current are prevented. Due to improved dielectric characteristics of the TaON layer, increasing the surface area of the dielectric layer-for example, by forming a HSG layer-may not be required, thereby increasing a processing margin between adjacent capacitors.
    Type: Application
    Filed: January 2, 2001
    Publication date: November 1, 2001
    Inventors: Dong Woo Shin, Seung Joon Jeon