Abstract: An apparatus for manufacturing a pouch-type rechargeable battery includes a preforming portion forming a folding groove in a portion of a protrusion of the pouch-type rechargeable battery, a folding portion disposed on a rear end of the preforming portion and folding the protrusion along the folding groove, a rolling portion disposed on a rear end of the folding portion and pressing the folded protrusion, and a pressing portion disposed on a rear end of the rolling portion and fixing the folded protrusion.

Abstract: The present application can provide an electrode, a method of manufacturing an electrode, and a use of the electrode. The present application can provide an electrode without forming the fat edge portion while an insulating layer formed by overlapping with the electrode active material layer on the current collector layer of the electrode effectively secures the insulation required for the electrode. In addition, even when the electrode design model is changed, the present application can provide a manufacturing method capable of manufacturing the above-described electrode by flexibly responding to the relevant change. In addition, the present application can provide a use of the electrode.

Abstract: An encoding/decoding apparatus and method for controlling a channel signal is disclosed, wherein the encoding apparatus may include an encoder to encode an object signal, a channel signal, and rendering information for the channel signal, and a bit stream generator to generate, as a bit stream, the encoded object signal, the encoded channel signal, and the encoded rendering information for the channel signal.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can duplicate modules so as to satisfy a performance level d (pl-d) required for the functional satisfy of a robot.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can duplicate modules so as to satisfy a performance level d (pl-d) required for the functional satisfy of a robot.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can generate a safety zone which is a zone to sense whether an obstacle is present.

Abstract: The motor for a washing machine according to the present invention comprises a motor housing 11 comprising a stator 12; a pair of first supports 16 formed integrally with the motor housing 11 in the front of the motor housing 11; a connection cylindrical member 11B cylindrically extending backwardly from a middle part of the motor housing 11 to be formed integrally with the motor housing 11; and a pair of second supports 21 integrally formed at right and left ends of the connection cylindrical member 11B.

Abstract: The present invention relates to a pharmaceutical composition for preventing or treating cancer, containing a mTOR-signaling inhibitor as an active ingredient. The composition of the present invention exhibits the efficacy of inhibiting the growth of cancer cells and killing cancer cells, and thus can be used as an anticancer agent.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: Semiconductor devices as described herein may include a fin-shaped pattern extending in a first direction, first and second side walls facing each other, first and second gate electrodes extending in a second direction and spaced apart from each other, a first gate spacer that is on a side wall of the first gate electrode, a second gate spacer that is on a side wall of the second gate electrode, a first trench in the fin-shaped pattern that is between the first and second gate electrodes and having a first width, and a second trench in the fin-shaped pattern that is below the first trench and has a second width smaller than the first width. The fin-shaped pattern may include first and second inflection points on the side walls of the fin-shaped pattern, and a bottom surface of the second trench may be lower than the inflection points.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: Semiconductor devices as described herein may include a fin-shaped pattern extending in a first direction, first and second side walls facing each other, first and second gate electrodes extending in a second direction and spaced apart from each other, a first gate spacer that is on a side wall of the first gate electrode, a second gate spacer that is on a side wall of the second gate electrode, a first trench in the fin-shaped pattern that is between the first and second gate electrodes and having a first width, and a second trench in the fin-shaped pattern that is below the first trench and has a second width smaller than the first width. The fin-shaped pattern may include first and second inflection points on the side walls of the fin-shaped pattern, and a bottom surface of the second trench may be lower than the inflection points.

Abstract: A semiconductor device is provided including first and second active fin arrays on a substrate. The semiconductor device further includes a pair of first gate spacers disposed on the first and second active fin arrays, each of the pair of first gate spacers including a first region having a first width, a second region having a second width, and a third region between the first region and the second region and having a third width; and first and second gate electrodes, the first gate electrode disposed between the first regions and the second gate electrode disposed between the second regions. The first regions are on the first active fin array, the second regions are on the second active fin array, and the third regions are between the first active fin array and the second active fin array. Each of the first and second widths is greater than the third width.

Abstract: There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.