Abstract: A semiconductor device includes a first processor configured to generate a first error check code of a first data and an audio circuitry. The audio circuitry is configured to receive the first data, receive a second data, generate a second error check code of the first data, and generate a modulation signal based on the first and second data. The first processor may determine whether the first and second error check codes are identical to each other. The first processor may control the audio circuitry to control the generation of the modulation signal based on at least the first data, in response to a determination that the first and second error check codes are identical to each other.

Abstract: A semiconductor device includes a first processor configured to generate a first error check code of a first data and an audio circuitry. The audio circuitry is configured to receive the first data, receive a second data, generate a second error check code of the first data, and generate a modulation signal based on the first and second data. The first processor may determine whether the first and second error check codes are identical to each other. The first processor may control the audio circuitry to control the generation of the modulation signal based on at least the first data, in response to a determination that the first and second error check codes are identical to each other.

Abstract: A semiconductor device includes a first processor configured to generate a first error check code of a first data and an audio circuitry. The audio circuitry is configured to receive the first data, receive a second data, generate a second error check code of the first data, and generate a modulation signal based on the first and second data. The first processor may determine whether the first and second error check codes are identical to each other. The first processor may control the audio circuitry to control the generation of the modulation signal based on at least the first data, in response to a determination that the first and second error check codes are identical to each other.

Abstract: A semiconductor device includes a first processor configured to generate a first error check code of a first data and an audio circuitry. The audio circuitry is configured to receive the first data, receive a second data, generate a second error check code of the first data, and generate a modulation signal based on the first and second data. The first processor may determine whether the first and second error check codes are identical to each other. The first processor may control the audio circuitry to control the generation of the modulation signal based on at least the first data, in response to a determination that the first and second error check codes are identical to each other.

Abstract: A signal processing method and apparatus are provided. A method of serializing signals output from an image sensor is provided which includes sampling a vertical synchronization signal, a horizontal synchronization signal, and parallel image data output from the image sensor, at a first edge of a clock signal, for n cycles of the clock signal, where n is an integer. The method further includes generating a packet including information regarding timing parameters and valid image data based on the sampling result.

Abstract: A signal processing method and apparatus are provided. A method of serializing signals output from an image sensor is provided which includes sampling a vertical synchronization signal, a horizontal synchronization signal, and parallel image data output from the image sensor, at a first edge of a clock signal, for n cycles of the clock signal, where n is an integer. The method further includes generating a packet including information regarding timing parameters and valid image data based on the sampling result.

Abstract: A circuit for providing image data for display can include a signal conversion unit configured to receive JPEG decompressed image data organized as horizontal block lines of an image directly from a JPEG compliant decoding unit.

Abstract: A bit stream processing apparatus is provided which stores a bit stream in a circular buffer without separately storing a header and data of the bit stream. The bit stream processing apparatus includes: a circular buffer for storing a transmitted bit stream; a first register for indicating a first read point of the bit stream stored in the circular buffer; a first backup register for backing up data stored in the first register; a second register for storing the number of bits to be read from the circular buffer; an adder for adding the data stored in the second register and data stored in a second register; a controller for determining the number of bits to be shifted in response to the output of the adder; a third register for storing data indicative of a number of bits to be ignored from the first read point; and a second backup register for backing up data stored in the third register.

Abstract: A bit stream processing apparatus is provided which stores a bit stream in a circular buffer without separately storing a header and data of the bit stream. The bit stream processing apparatus includes: a circular buffer for storing a transmitted bit stream; a first register for indicating a first read point of the bit stream stored in the circular buffer; a first backup register for backing up data stored in the first register; a second register for storing the number of bits to be read from the circular buffer; an adder for adding the data stored in the second register and data stored in a second register; a controller for determining the number of bits to be shifted in response to the output of the adder; a third register for storing data indicative of a number of bits to be ignored from the first read point; and a second backup register for backing up data stored in the third register.