Patents by Inventor Seung Kang

Seung Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070287287
    Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 13, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Seung KANG, Jun SEO, Min-Chul CHAE, Jae-Seung HWANG, Sung-Un KWON, Woo-Jin CHO
  • Publication number: 20070223561
    Abstract: Disclosed herein is a working electrode structure of a biosensor, in which the shape of one end of the working electrode including a reaction portion is modified to have different electrode widths for each section along a lengthwise direction within the reaction portion, so that although there is caused a length error in the reaction portion of the working electrode in the process of fixing a reagent during the fabrication of the electrode, an error for an area of the reaction portion can be restricted at the maximum, which results in a reduction in measurement error and an improvement in measurement reliability.
    Type: Application
    Filed: May 15, 2006
    Publication date: September 27, 2007
    Inventors: Yon Ahn, Jun Ryu, Seung Kang
  • Publication number: 20070180266
    Abstract: A digital cryptograph and encryption process encrypts and transmits in a digital format specific items of information requested by a user of a digital content transmission system by using key information, a user's key and a temporary validation key, to decrypt and replay the encrypted digital information at the user's terminal by using the key information and the user's authorization information. Each registered subscribing user is provided with unique key information. The user key is generated by applying the key information to a key generation algorithm. The temporary validation key that is created when the registered user accesses the server, is encrypted with the user key. The digital information is encrypted by using the temporary validation key in an encryption algorithm. The decryption algorithm allows the user to decrypt and replay the encrypted digital information upon receipt of the key information that has a one-to-one correspondence to the identity characters of the registered subscribing user.
    Type: Application
    Filed: December 15, 2006
    Publication date: August 2, 2007
    Inventors: En-Seung Kang, Jin-Young Byun
  • Publication number: 20070168818
    Abstract: A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.
    Type: Application
    Filed: February 12, 2007
    Publication date: July 19, 2007
    Applicant: Agere Systems, Inc.
    Inventors: Seung Kang, Subramanian Karthikeyan, Sailesh Merchant, Lisa Mullin
  • Publication number: 20070150098
    Abstract: An apparatus for controlling a robot and a method thereof are provided. The apparatus includes: a state interpretation unit determining whether or not a current situation belongs to a preset unstable state by evaluating the current situation based on a plurality of perception information items; and a target generation unit setting a target action of the robot by comparing the current situation and the determination result with a predetermined value system, and then, modifying the target action by receiving a feedback of the action performance result of the robot as perception information. According to the method and apparatus, by inputting a processing procedure and a value system to solve a variety of unstable states that can occur in situations of a user and circumstances surrounding the robot, the robot can actively respond with actions.
    Type: Application
    Filed: November 1, 2006
    Publication date: June 28, 2007
    Inventors: Min Su Jang, Joo Chan Sohn, Young Cheol Go, Sang Seung Kang, Young Jo Cho
  • Publication number: 20070116948
    Abstract: An adhesive film and a method of fabricating a flexible display using the same are provided. The adhesive film includes: a support including a first surface disposed opposite to a flexible substrate for forming an image display element and a second surface disposed opposite to a support substrate for supporting the flexible substrate; a first adhesive material applied on the first surface of the support; and a second adhesive material applied on the second surface of the support and having a greater adhesive strength than the first adhesive material. The flexible substrate can be easily detached from the support substrate, so that the flexible display can be realized in various sizes and thicknesses using existing equipment without modification of mass-production equipment for realizing the flexible display.
    Type: Application
    Filed: June 28, 2006
    Publication date: May 24, 2007
    Inventors: Gi Kim, Yong Kim, In You, Kyu Baek, Seung Kang, Seong Ahn, Kyung Suh
  • Publication number: 20070093004
    Abstract: Provided is a method of manufacturing a thin film transistor (TFT) including a transparent ZnO thin layer that is formed at a low temperature by causing a surface chemical reaction between precursors containing elements constituting the ZnO thin layer. The method includes the steps of: depositing a gate metal layer on a substrate and forming a gate electrode using photolithography and selective etching processes; depositing a gate insulator on the substrate having the gate electrode; forming source and drain electrodes; and depositing a ZnO thin layer on the gate insulator using a surface chemical reaction between precursors containing elements constituting the ZnO thin layer.
    Type: Application
    Filed: July 19, 2006
    Publication date: April 26, 2007
    Inventors: Sang Park, Chi Hwang, Hye Chu, Jeong Lee, Jin Lee, Ho Kwack, Yong Lee, Seung Kang
  • Publication number: 20070082138
    Abstract: A surface treatment method of an FRP substrate is provided. According to the method, an FRP substrate that is less deformed than a conventional flexible substrate material is used, and surface roughness, which is a drawback of the FRP substrate, is improved so that it may be applied to the fabrication of a device. In order to reduce the surface roughness of an FRP substrate, the FRP substrate is coated with an organic insulating solution and thereby planarized. Due to the reduced deformation and superior flatness, failures occurring due to misalignment in a photolithography process may be prevented.
    Type: Application
    Filed: June 8, 2006
    Publication date: April 12, 2007
    Inventors: In You, Seung Kang, Seong Ahn, Gi Kim, Ji Oh, Chul Kim, Kyu Baek, Kyung Suh
  • Publication number: 20070069365
    Abstract: Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.
    Type: Application
    Filed: September 28, 2005
    Publication date: March 29, 2007
    Inventors: Vance Archer, Daniel Chesire, Seung Kang, Taeho Kooh, Sailesh Merchant
  • Publication number: 20070069394
    Abstract: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.
    Type: Application
    Filed: July 21, 2006
    Publication date: March 29, 2007
    Applicant: Agere Systems Inc.
    Inventors: Mark Bachman, Donald Bitting, Sailesh Chittipeddi, Seung Kang, Sailesh Merchant
  • Publication number: 20070069368
    Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 29, 2007
    Inventors: Vance Archer, Kouros Azimi, Daniel Chesire, Warren Gladden, Seung Kang, Taeho Kook, Sailesh Merchant, Vivian Ryan
  • Publication number: 20070063352
    Abstract: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 22, 2007
    Applicant: Agere Systems Inc.
    Inventors: Vance Archer, Michael Ayukawa, Mark Bachman, Daniel Chesire, Seung Kang, Taeho Kook, Sailesh Merchant, Kurt Steiner
  • Patent number: 7178022
    Abstract: A digital cryptograph and encryption process encrypts and transmits in a digital format specific items of information requested by a user of a digital content transmission system by using key information, a user's key and a temporary validation key, to decrypt and replay the encrypted digital information at the user's terminal by using the key information and the user's authorization information. Each registered subscribing user is provided with unique key information. The user key is generated by applying the key information to a key generation algorithm. The temporary validation key that is created when the registered user accesses the server, is encrypted with the user key. The digital information is encrypted by using the temporary validation key in an encryption algorithm. The decryption algorithm allows the user to decrypt and replay the encrypted digital information upon receipt of the key information that has a one-to-one correspondence to the identity characters of the registered subscribing user.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: February 13, 2007
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: En-Seung Kang, Jin-Young Byun
  • Publication number: 20070033555
    Abstract: Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.
    Type: Application
    Filed: August 5, 2005
    Publication date: February 8, 2007
    Inventors: Kausar Banoo, Seung Kang, Shahriar Moinian, Blane Musser, John Pantone
  • Publication number: 20070023794
    Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
    Type: Application
    Filed: July 13, 2006
    Publication date: February 1, 2007
    Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
  • Patent number: 7159126
    Abstract: A digital cryptograph and encryption process encrypts and transmits in a digital format specific items of information requested by a user of a digital content transmission system by using key information, a user's key and a temporary validation key, to decrypt and replay the encrypted digital information at the user's terminal by using the key information and the user's authorization information. Each registered subscribing user is provided with unique key information. The user key is generated by applying the key information to a key generation algorithm. The temporary validation key that is created when the registered user accesses the server, is encrypted with the user key. The digital information is encrypted by using the temporary validation key in an encryption algorithm. The decryption algorithm allows the user to decrypt and replay the encrypted digital information upon receipt of the key information that has a one-to-one correspondence to the identity characters of the registered subscribing user.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: January 2, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: En-Seung Kang, Jin-Young Byun
  • Publication number: 20060283198
    Abstract: An apparatus and a method for controlling the operation of a unitary air conditioner, which diversify signals to be transmitted using existing connection lines for transmitting signals by adjusting an interval between ON and OFF signals, etc., thereby allowing the unitary air conditioner to be operated in various modes.
    Type: Application
    Filed: March 13, 2006
    Publication date: December 21, 2006
    Applicant: LG Electronics Inc.
    Inventors: Chan Song, Seung Hyun, Jeong Park, Seung Kang
  • Publication number: 20060281290
    Abstract: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 14, 2006
    Inventors: Jong-Seon Ahn, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Eun-Kuk Chung, Hyung-Mo Yang, Chang-Yeon Yoo, Yun-Seung Kang, Kyung-Tae Jang
  • Publication number: 20060191265
    Abstract: A cogeneration system is disclosed, wherein a generator which generates electricity, a drive source which operates to drive the generator, and generates waste heat during the operation of the drive source, a waste heat recoverer which recovers the waste heat of the drive source, and a radiator which radiates the waste heat recovered by the waste heat recoverer are arranged in a single chassis. The cogeneration system has a compact and simple arrangement, and achieves simple control operations, and an enhancement in operability.
    Type: Application
    Filed: June 20, 2005
    Publication date: August 31, 2006
    Applicant: LG Electronics Inc.
    Inventors: Seung Kang, Chang Choi, Won Choi, Hyung Lim, Yoon Hwang
  • Publication number: 20060192584
    Abstract: Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.
    Type: Application
    Filed: April 13, 2006
    Publication date: August 31, 2006
    Inventors: Seung Kang, Subramanian Karthikeyan, Sailesh Merchant