Abstract: An omnidirectional speaker includes a speaker module configured to generate sound, a main body having a circular cross section and configured to accommodate the speaker module, and a control panel configured to cover an upper side of the main body and allow a user to select an operation. The control panel includes a display for displaying a state of the operation and a touch unit configured to receive an input of the user as a touch input.

Abstract: An omnidirectional speaker includes a speaker module configured to generate sound, a main body having a circular cross section and configured to accommodate the speaker module, and a control panel configured to cover an upper side of the main body and allow a user to select an operation. The control panel includes a display for displaying a state of the operation and a touch unit configured to receive an input of the user as a touch input.

Abstract: A data output device is disclosed having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal, first and second logic units for performing logic operations with respect to pre-flag signals and data inversion flag signals, a first output unit for inverting or non-inverting and outputting a plurality of bits contained in the first output data in response to the first data inversion flag signal, a second output unit for inverting or non-inverting and outputting a plurality of bits contained in the second output data in response to the second data inversion flag signal, and an output data initializer for, when a no-operation period is generated in a series of data output operations, initializing the arbitrary output data and supplying the resulting data to the first comparator.

Abstract: A precharge circuit prevents voltage dropping of a local input/output line in a semiconductor memory apparatus. The precharge circuit includes at least one pair of pull-up and pull-down precharge circuits. When a local input/output line precharge signal is enabled, a precharge voltage to be applied to each of the precharge circuits is supplied to a local input/output line and a local input/output line-bar. The pull-up precharge circuit has P-type MOS transistors, and the pull-down precharge circuit has N-type transistors. With this configuration, dropping of precharge voltage levels of local input/output lines can be prevented, thus improving reliability of the memory apparatus.

Abstract: A data output device and method is disclosed, the device having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal which is enabled or disabled according to the number of bits of the first output data having made level transitions, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal which is enabled or disabled according to the number of bits of the second output data having made level transitions, first and second logic units for performing logic operations with respect to pre-flag signals and data inversion flag signals, a first repeater for inverting or non-inverting and outputting a plurality of bits contained in the first output data in response to the first data inversion flag signal, and a second repeater for inverting or non-inverting and outputting a plurality of bits contained in the second output data in response to the sec

Abstract: A data output device is disclosed having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal, first and second logic units for performing logic operations with respect to pre-flag signals and data inversion flag signals, a first output unit for inverting or non-inverting and outputting a plurality of bits contained in the first output data in response to the first data inversion flag signal, a second output unit for inverting or non-inverting and outputting a plurality of bits contained in the second output data in response to the second data inversion flag signal, and an output data initializer for, when a no-operation period is generated in a series of data output operations, initializing the arbitrary output data and supplying the resulting data to the first comparator.

Abstract: Disclosed is an internal voltage supplier for the memory device, the internal voltage supplier comprising: a first switching means for selecting one of a first voltage generated from an interior of the memory device and a second voltage applied from an exterior of the memory device; and a divider for receiving the first voltage or the second voltage selected by the first switching means and outputting a plurality of internal voltages.

Abstract: Provided is directed to a circuit for controlling data and a data strobe driver in a semiconductor memory device, including: a first delay unit for outputting a data signal with a variable delay; a DQ driver for outputting a data signal according to the data signal passed through the first delay unit and a driver select signal; a second delay unit for outputting a data strobe signal with a variable delay; and a DQS driver for outputting the data strobe signal passed through the second delay unit by being driven according to the driver select signal.