Abstract: Various embodiments of the present invention relate to a secondary battery, and the objective of the present invention is to provide a secondary battery, which has drop-impact resistance, by providing an electrode assembly having a relatively thick inner circumferential and a relatively thin outer circumferential tab. To this end, disclosed is a secondary battery, which comprises an electrode assembly comprising: an anode plate having an inner circumferential tab formed at a wound front end thereof; a separator covering the anode plate; and a cathode plate having an outer circumferential tab formed at a wound distal end thereof.

Abstract: Disclosed herein are a method for countering an asynchronous attack on a supply chain security protocol and an apparatus for the same. The method includes, in a supply chain security protocol performed by a terminal device into which a dielet is inserted and an authentication server, performing a self-generation mode in which a counter value within the dielet is registered in the authentication server, performing a read-out mode in which whether an asynchronous attack occurs is detected by comparing the counter values respectively stored in the dielet and the authentication server when a message for communication is sent, and replacing a message for the communication with a random value when an asynchronous attack is detected.

Abstract: Various embodiments of the present invention relate to a secondary battery, and the objective of the present invention is to provide a secondary battery, which has drop-impact resistance, by providing an electrode assembly having a relatively thick inner circumferential and a relatively thin outer circumferential tab. To this end, disclosed is a secondary battery, which comprises an electrode assembly comprising: an anode plate having an inner circumferential tab formed at a wound front end thereof; a separator covering the anode plate; and a cathode plate having an outer circumferential tab formed at a wound distal end thereof.

Abstract: Disclosed are an encryption database device, method, and system. The encryption database device includes a memory configured to store and read information, and a processor configured to control the storing and reading of the memory, wherein the processor is configured to allocate blocks to the memory and store at least one ciphertext for plaintext for each of the blocks, generate mapping information associating order information of the plaintext with block information obtained by encrypting a start position of the block in which the ciphertext is stored, access the block associated with the order information corresponding to a search range of the plaintext requested by a client using the mapping information, and respond with information related to the ciphertext of the accessed block to the client.

Abstract: Disclosed herein is a method for encoding order information. The method may include generating multiple binary trees, preparing multiple different secret keys, determining a binary tree corresponding to any one secret key selected from among the multiple secret keys, and encoding the order information of the determined binary tree.

Abstract: Disclosed herein are a hardware security module, a device having the hardware security module, and a method for operating the device. The method for verifying integrity of executable code in a device includes dividing, by a Micro-Control Unit (MCU), executable code into multiple blocks, generating, by the MCU, hash values corresponding to the blocks resulting from the division, storing, by a Hardware Security Module (HSM), the generated hash values, calculating, by the MCU, at least one hash value, among hash values of the multiple blocks when the executable code boots, and comparing, by the HSM, the calculated hash value with a hash value corresponding to the calculated hash value, among the hash values stored in the HSM.

Abstract: Disclosed herein are an apparatus and method for calculating a multiplicative inverse. The apparatus for calculating a multiplicative inverse includes a data input unit for receiving input data, a multiplicative inverse calculation unit for dividing an input degree-8 finite field corresponding to the input data into two first degree-4 finite fields so as to perform Advanced Encryption Standard (AES) encryption on the input data, and for performing a multiplicative inverse calculation on the first degree-4 finite fields in consideration of a circuit depth value (T-Depth) and qubit consumption of quantum gates in a quantum circuit, and a data output unit for outputting result data obtained by performing the multiplicative inverse calculation.

Abstract: Disclosed herein are a white-box encryption method for preventing a fault injection attack and an apparatus for the same. The white-box encryption method is configured to acquire a first intermediate value by inputting plaintext to a first part, among all of rounds of a white-box-based encryption algorithm, before table redundancy operations are performed, to input the first intermediate value to a second part for performing the table redundancy operations through at least two lookup tables to which different encodings based on a secret key are applied, among all of the rounds, to acquire a second intermediate value by inputting the output values of the at least two lookup tables to at least one XOR lookup table, and to output ciphertext for the plaintext based on a third part for decoding the second intermediate value.

Abstract: Disclosed herein are a hardware security module, a device having the hardware security module, and a method for operating the device. The method for verifying integrity of executable code in a device includes dividing, by a Micro-Control Unit (MCU), executable code into multiple blocks, generating, by the MCU, hash values corresponding to the blocks resulting from the division, storing, by a Hardware Security Module (HSM), the generated hash values, calculating, by the MCU, at least one hash value, among hash values of the multiple blocks when the executable code boots, and comparing, by the HSM, the calculated hash value with a hash value corresponding to the calculated hash value, among the hash values stored in the HSM.

Abstract: A secret information generation apparatus and a method for operating the secret information generation apparatus. The secret information generation apparatus includes a resistor-capacitor circuit, and a microcontroller unit including a first pin connected to an input terminal of the resistor-capacitor circuit and a second pin connected to an output terminal of the resistor-capacitor circuit, wherein the microcontroller unit is configured to transmit a digital value corresponding to a challenge to the resistor-capacitor circuit through the first pin, receive an output value of the resistor-capacitor circuit corresponding to the digital value through the second pin, convert the received value into a digital value using an analog-to-digital converter, extract one or more valid bits from the converted digital value, and then generate a response.

Abstract: Provided is a white-box cryptography method and apparatus for preventing side channel analysis. An input plain text is encrypted and output according to white-box cryptography and, in this case, the value output according to the encryption includes a first value corresponding to a value obtained by masking an intermediate value obtained by encrypting the plain text with a mask and a second value corresponding to the mask.

Abstract: An encrypting apparatus includes a storage unit and a controller. The storage unit stores an encryption algorithm including an internal function outputting a second value from a first value and an inversion mode encryption algorithm including an inversion mode internal function outputting a complement of the second value from a complement of the first value. The controller selects one of an inversion mode and a non-inversion mode. The controller outputs a cipher text from a plain text using the encryption algorithm when the non-inversion mode is selected.

Abstract: Provided are an operation method and a secure terminal for performing the method. The operation method may include receiving, from a user terminal, a plain text on which an external encoding operation is to be performed, performing the external encoding operation on the plain text, and transmitting the external encoding operated plain text to the user terminal, and the operation method may include receiving, from a user terminal, a cryptogram in which a white-box cryptography operation is performed on an external encoding operated plain text; performing an external decoding operation on the cryptogram; and transmitting the external decoding operated cryptogram to the user terminal.

Abstract: A side channel analysis apparatus based on a profile includes a waveform collection unit configured to collect leaked information from a target device of a side channel analysis; and a preprocessing unit configured to preprocess a waveform data correspond to the leaked information collected from the waveform collection unit before analyzing same. Further, the side channel analysis apparatus includes an analysis unit configured to analyze the waveform data preprocessed in the preprocessing unit; and a profile configuration unit configured to make each process of the waveform collection unit, the preprocessing unit, and the analysis unit into a process and configure a profile for managing each process by connection of each process.

Abstract: Provided is an encoding apparatus including a communication unit configured to receive data from an outside, a memory configured to store an instruction for encoding the data, and a processor configured to encode the data according to the instruction, in which the instruction includes an instruction for encoding the data using a first table for looking up and calculating a result value obtained by encoding according to a predetermined pattern in an a-th round, and when among first to fourth data included in data obtained by encoding through the first table, an i-th bit of exclusive OR of the second to fourth data and a j-th bit of the first data are different, an instruction for encoding the data using a second table for looking up and calculating a result value calculated by performing additional encoding on exclusive OR of the first to fourth data.

Abstract: A white box encryption device is provided. The device included in a second device among a first device and the second device performing wired or wireless communication, and performing an encryption/decryption operation using a white box encryption table consisting of a look-up table set, includes, a non-volatile memory configured to store an incomplete look-up table set in which at least one look-up table or a portion of entire look-up table is removed, a volatile memory configured to store the incomplete look-up table set received from the non-volatile memory and the at least one look-up table received from the first device at a time of the encryption/decryption operation, and construct a complete look-up table set, and an encryption/decryption operation unit configured to perform the encryption/decryption operation using the complete look-up table set.

Abstract: Disclosed are a white box encryption apparatus and method. The white box encryption method includes performing an encryption operation using a plurality of white box encryption tables for each of a plurality of rounds, and mixing arrangement of result tables output for each round.

Abstract: In accordance with an embodiment, the logical exclusive operation on the random number RAND and the OPc value are performed several times, the logical operation and encryption processing using a random number RAND and logical operation and encryption processing using a random number S are done in any order, which brings an increase of an attack complexity as to whether to calculate the correlation coefficient from the power consumption waveform at any point when analyzing the correlation power, whereby it is possible to defend the CPA attack effectively.

Abstract: Disclosed is a dual conversion apparatus for preventing a side channel analysis, including: a microcontroller which converts one-bit expression, which is expressed by zero and one, into one of two four-bit transitions, reconstructs a cryptographic algorithm, and applies the four-bit converted dual conversion to the reconstructed cryptographic algorithm; and a storing unit which stores the four-bit converted dual conversion which is converted by the microcontroller.

Abstract: Provided is an encoding apparatus including a communication unit configured to receive data from an outside, a memory configured to store an instruction for encoding the data, and a processor configured to encode the data according to the instruction, in which the instruction includes an instruction for encoding the data using a first table for looking up and calculating a result value obtained by encoding according to a predetermined pattern in an a-th round, and when among first to fourth data included in data obtained by encoding through the first table, an i-th bit of exclusive OR of the second to fourth data and a j-th bit of the first data are different, an instruction for encoding the data using a second table for looking up and calculating a result value calculated by performing additional encoding on exclusive OR of the first to fourth data.