Abstract: Integrated driver circuits include a pull-up circuit having a first plurality of PMOS pull-up transistors therein which are selectively enabled by a first multi-bit impedance control signal. This first multi-bit impedance control signal is a function of a first variable resistance device. A pull-down circuit is also provided. The pull-down circuit has a first plurality of NMOS pull-down transistors therein which are selectively enabled by a second multi-bit impedance control signal. This second multi-bit impedance control signal is a function of a resistance of a second variable resistance device. The pull-up circuit and pull-down circuit have commonly connected outputs. In particular, the pull-up circuit has a first impedance which is a function of a digital value of the first multi-bit impedance control signal and the pull-down circuit has a second impedance which is a function of a digital value of the second multi-bit impedance control signal.

Abstract: A level converter for use in a semiconductor memory device includes a level converting unit, a latch circuit and a blocking circuit. The level converting unit receives sensed first and second sensing voltages and a control clock and which provides level-converted first and second output voltages in correspondence with the first and second sensing voltage at first and second output nodes in response to the control clock. The latch circuit boosts a difference between the first and second output voltages provided at the first and second output nodes to be substantially equal to the level of a supply voltage in response to the application of the supply voltage. The blocking circuit controls the application of the supply voltage to the level converting unit and the latch circuit according to the control clock, in order to reduce current consumption due to the application of the supply voltage and to achieve a high operating speed.

Abstract: The present invention relates to an input buffer used in semiconductor memory devices and more particularly to an input buffer capable of operating at a high speed by using a BiCMOS (bi-complementary metal oxide semiconductor) circuit.

Abstract: A decoding circuit and method for a semiconductor memory device simplifies a decoding process by individually performing a large block decoding and small block decoding operations, and thereby reduces the total time delay taken in an address decoding process and layout area occupied by decoding circuits. The decoding circuit for a semiconductor memory device having a memory cell array including a plurality of large blocks, each large block including m small blocks (wherein m=2,3, . . . ) and having a plurality of memory cells being arranged in a matrix form, and a plurality of reading/writing circuits each corresponding to said large blocks, includes a first decoding circuit for receiving a first address to simultaneously select respective specific small block in each of the large blocks, corresponding to the first address, and a second decoding circuit for receiving a second address to enable a selected one of the reading/writing circuits corresponding to said second address.