Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

Abstract: An apparatus and method for treating a substrate are provided. The apparatus includes at least one first process chamber configured to supply a developer onto the substrate; at least one second process chamber configured to treat the substrate using a supercritical fluid; a transfer chamber configured to transfer the substrate from the at least one first process chamber to the at least one second process chamber, while the developer supplied in the at least one first process chamber remains on the substrate; and a temperature and humidity control system configured to manage temperature and humidity of the transfer chamber by supplying a first gas of constant temperature and humidity into the transfer chamber.

Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

Abstract: An immersed hollow fiber membrane module according to an embodiment of the present disclosure includes a hollow fiber membrane bundle formed by fixing a plurality of hollow fiber membranes by a potting agent, and a module supporting unit provided at one side of the hollow fiber membrane bundle to support the hollow fiber membrane bundle, the module supporting unit having an air cleaning time delaying portion configured to delay or intermittently maintain an air cleaning time for air introduced therein and discharged out.

Abstract: An immersed hollow fiber membrane module according to an embodiment of the present disclosure includes a hollow fiber membrane bundle formed by fixing a plurality of hollow fiber membranes by a potting agent, and a module supporting unit provided at one side of the hollow fiber membrane bundle to support the hollow fiber membrane bundle, the module supporting unit having an air cleaning time delaying portion configured to delay or intermittently maintain an air cleaning time for air introduced therein and discharged out.

Abstract: An ATM switch network with an expansible optical ring, in which each switch forms several paths with a vertical ring, a horizontal ring and an expansible ring. The network has a large-capacity and a small switching interval, minimizing cell delay deviation and rendering the network suitable for high-speed multimedia service. A group switch node is formed by grouping the switches forming the vertical and horizontal rings, thereby enhancing reliability within a transmission interval by bisecting the wavelength division multiplexed logical paths and by using two optical lines. The network discriminates between I/O terminals for matching data having a low-speed small capacity and wavelength division I/O terminals for matching data having a high-speed large capacity. By using a node's I/O terminals, the network interconnects nodes via wavelength division multiplexing optical lines, thereby forming an automatic adaptive network.