Abstract: A head-mounted device may have an inner display that displays images for a user and an outer display that informs nearby people of the status of the user and inner display. For example, the outer display may display an image of a face, an abstract layer, or both, depending on whether the inner display is operating in passthrough mode, mixed reality mode, or virtual reality mode. An ambient light sensor in the head-mounted device may be used to measure the brightness and color of ambient light. The white point of the face layer on the outer display may be adapted to the color of ambient light, whereas the white point of the abstract layer on the outer display may remain fixed. The white point of a display may be a correlated color temperature setting (e.g., measured in degrees Kelvin) that determines the warmth or coolness of displayed colors.

Abstract: A repair circuit for integrated circuits adapted for selecting and repairing a storage cell having a fault, and a main fuse adapted for operating the repair circuit. The repair circuit comprises a plurality of p-channel MOSFETs and a plurality of fuses. A NAND gate has as inputs, an output signal from said repair circuit and a control signal. The control signal is generated as the address of the selected cell is varied. The control signal is a pulse which transits from a low lever to a high level and back to a low level again as the address is varied. The repair circuit reduces power consumption in integrated circuits by allowing current to flow therein only when the address of the selected cell is varied.

Abstract: An output buffer circuit for an integrated circuit for outputting an amplified signal from a sense amplifier which senses information stored in a memory cell of random access memory for improving operation of the integrated circuit is disclosed. The output buffer circuit comprises NAND gates ND1, ND2 operatively connected to the output of the sense amplifier to receive first and second output signals S1, S2, and operatively connected to receive a control signal .phi.1 from the integrated circuit which operates the memory cell to read. A MOSFET Q1 and a MOSFET Q2 are utilized with both MOSFETs turning on or off depending upon the signals applied to their gates. An output loading capacitor CL is operatively connected to the junction P4 and to the ground. A logic combination means 10 connected to junctions P1, P2 performs a logical combination of the signal applied through the junction P4 and the control signal .phi.1 applied to the input points of the logic combination means.