Abstract: A composition for preventing or treating peripheral T-cell lymphoma includes a compound represented by formula 1 or pharmaceutically acceptable salts thereof. Specifically, a pharmaceutical composition based on the composition is capable of effectively ameliorating peripheral T-cell lymphoma by decreasing regulatory T cells and increasing CD8+ T cells. The pharmaceutical composition may exhibit anticancer activity against peripheral T-cell lymphoma by decreasing regulatory T cells which suppress immune responses and increasing CD8+ T cells which exhibit anticancer activity. In addition, the pharmaceutical composition is used for the treatment of peripheral T-cell lymphoma due to excellent safety and tolerability.

Abstract: A repair circuit for integrated circuits adapted for selecting and repairing a storage cell having a fault, and a main fuse adapted for operating the repair circuit. The repair circuit comprises a plurality of p-channel MOSFETs and a plurality of fuses. A NAND gate has as inputs, an output signal from said repair circuit and a control signal. The control signal is generated as the address of the selected cell is varied. The control signal is a pulse which transits from a low lever to a high level and back to a low level again as the address is varied. The repair circuit reduces power consumption in integrated circuits by allowing current to flow therein only when the address of the selected cell is varied.

Abstract: An output buffer circuit for an integrated circuit for outputting an amplified signal from a sense amplifier which senses information stored in a memory cell of random access memory for improving operation of the integrated circuit is disclosed. The output buffer circuit comprises NAND gates ND1, ND2 operatively connected to the output of the sense amplifier to receive first and second output signals S1, S2, and operatively connected to receive a control signal .phi.1 from the integrated circuit which operates the memory cell to read. A MOSFET Q1 and a MOSFET Q2 are utilized with both MOSFETs turning on or off depending upon the signals applied to their gates. An output loading capacitor CL is operatively connected to the junction P4 and to the ground. A logic combination means 10 connected to junctions P1, P2 performs a logical combination of the signal applied through the junction P4 and the control signal .phi.1 applied to the input points of the logic combination means.