Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

Abstract: An integrated circuit including: a first cell including first-a and second-a output pins, a first routing wire connecting the first-a output pin to the second-a output pin, a first-a via connecting the first-a output pin to the first routing wire, and a second-a via connecting the second-a output pin to the first routing wire; and a second cell including first-b and second-b output pins, a second routing wire connecting the first-b output pin to the second-b output pin, a first-b via connecting the first-b output pin to the second routing wire, and a second-b via connecting the second-b output pin to the second routing wire, wherein the first-a via is at a first-a position, the second-a via is at a second-a position, the first-b via is at a first-b position, the second-b via is at a second-b position different from each other.

Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

Abstract: Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

Abstract: A layout method is provided. The layout method may include placing first and second standard cells from a standard cell library, interconnecting the placed standard cells to generate a layout draft, confirming placement and routing at a boundary region between the interconnected standard cells, and revising the layout draft based on the confirmation. Each of the standard cells includes, in part, a conductive line that extends in the first direction and is interconnected to an adjacent standard cell through a source/drain via. To confirm the placement and routing, a first spaced distance from a tip of one of the conductive lines to a tip of the other conductive line, and a second spaced distance from the tip of the first conductive line to the cell boundary are compared with preset threshold values. Revising the layout draft may include adjusting a tip position of one of the conductive lines.

Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

Abstract: Provided is a surface acoustic wave (SAW) sensor sensing pressure, temperature, etc., by using a SAW. The SAW sensor includes: a substrate having one of its surfaces formed with a cavity having a predetermined depth; a piezoelectric plate which has piezoelectricity, so as to make a SAW, and which is adhered to the surface in which the cavity is formed, so as to cover the cavity of the substrate; a pressure resonator which is installed to a portion of the piezoelectric plate that corresponds to the cavity groove, and which generates a SAW due to a radio frequency (RF) signal applied thereto; and a reference resonator which is installed to the piezoelectric plate to be outside the portion corresponding to the cavity and be parallel to the pressure resonator, and which generates a SAW due to the RF signal applied thereto.