Abstract: A method of mounting a bus-bar frame includes: forming a plurality of cell lead blocks and a battery cell stacked body by alternately stacking a cell lead block and at least one battery cell; disposing a top cover with respective ends on which a bus-bar frame is installed so as to cover the battery cell stacked body; removing the lead blocks from a space between the battery cell stacked body and the bus-bar frame; and installing the bus-bar frame on the battery cell stacked body by rotating the bus-bar frame. The alternately stacking of the cell lead block and the at least one battery cell includes positioning an electrode lead protruding from each battery cell between neighboring ones of the cell lead blocks.

Abstract: A graphic RAM array has a plurality of sub blocks which share random and serial output paths. This structure enables random access to the random output path of one RAM array while a specific sub block of another other RAM array is performing a display operation via the serial output path. The graphic RAM does not have a separate data register and outputs the serial data using only the RAM array. Thus, only the RAM array is formed in the cell core region, thereby reducing the size and price of the chip. In addition, it is possible for the graphic RAM to be compatible with a system having a conventional video RAM controller.

Abstract: A video RAM having a random access memory, a serial access memory, and a block selector for high speed data processing is disclosed. A serial write transfer operation for transferring data stored in the serial access memory to the random access memory is performed by writing the serial write data on all serial access memory blocks and then transmitting, the serial write data selectively to the desired blocks of the random access memory.

Abstract: An improved sense amplifier driver for sensing and restoring data in memory cells is disclosed. Pull-up means in the form of p-channel MOS transistors are respectively provided for forcibly pulling up the gate voltage of delayable p-channel MOS transistors within the first inverter of the sensing clock driver and the second inverter of the restore clock driver in the trailing transient periods of the sensing and restoring clock signals. The formation of a DC current path between the power line and the ground line in any one of the delayable p-channel MOS transistors is prevented, thereby making it possible to avoid the unnecessary power dissipation. Further, delaying resistances are installed respectively in the first inverter of the sensing clock driver and in the second inverter of the restoring clock driver to make the slope of the leading edges of the sensing and restoring clocks less steep, thereby making it possible to exclude the occurrence of noise.

Abstract: A dynamic random access memory for substituting a normal column line coupled for faulty normal memory cells for a spare column line coupled to defect-free spare memory cells with a latch having a master fuse and an input terminal coupled to a reset clock, a spare column decoder enabling or disabling the spare column line with the output of the latch and the selective input of either true column address signals or complement column address signals and a plurality of normal column decoders enabling or disenabling normal column lines with the column address signals addressing a specified normal column line under the control of the ouptut of the spare column decoder.

Abstract: A data transmission circuit for CMOS dynamic random access memory devices having a data input buffer for converting TTL input data signals to CMOS logic level data signals and providing true and complement data signals on a pair of data bus lines, a pair of transmission gates for transmitting the true and complement data signals to a pair of true and complement I/O bus lines comprising a pair of similar constitutional I/O bus line pull-up or pull-down circuits between the output lines of the transmission gates and the I/O bus lines for making logic operations on the data bus lines. The I/O bus lines alternate at the time of a writing operation and a I/O bus line equalizing circuit is connected between the true and complement I/O bus lines for equalizing the pair of the I/O bus lines at a high speed, before or after a writing cycle.