Abstract: The present disclosure relates to a carbonic anhydrase complex and a method for preparing same, in which a conjugate of a carbonic anhydrase and a dockerin module is bound to a small cellulose binding protein including a cohesin module and a cellulose binding module (CBM) and method of manufacturing thereof. The complex, which includes a cellulose binding module, is immobilized on the surface of green algae, to increase access to a substrate and enzyme activity, thereby efficiently fixing carbon dioxide, and increasing the growth and lipid production of green algae without adding other carbon sources. The present disclosure is expected to be actively utilized in fields, such as biofuels, using carbon dioxide fixation.

Abstract: A storage device includes a nonvolatile memory; a controller configured to control a write operation of the nonvolatile memory according to a write request received from a host and transmit a response to the write request to the host; and write buffers configured to store write data received with the write request. The controller is further configured to: set a response transmission delay time based on an available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time, transmit the response to the write request to the host after the response transmission delay time passes, and dynamically adjust, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller for controlling a plurality of memory devices in which data is stored may include a host interface configured to receive a request and a logical address corresponding to the request from a host, a processor including multiple cores, each configured to receive the logical address from the host interface and generate mapping information indicating a mapping relationship between the logical address and a physical address and a bitmap storage configured to store a bitmap indicating which core of the multiple cores each of previously-received logical addresses is assigned, wherein the host interface assigns the logical address to one of the multiple cores based on the bitmap.

Abstract: A memory system includes a memory device configured to store data through a write operation and output the stored data as read data through a read operation; a buffer memory configured to store the read data output from the memory device; a controller configured to control the memory device such that the memory device performs the read operation in response to a read request received from a host, and to control the buffer memory to store the read data in the buffer memory. When the read request corresponds to an asynchronous read operation, the controller may allocate a partial area of the buffer memory as storage space for the read data after the read operation of the memory device is completed.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including buffer blocks and main blocks, and a memory controller configured to control the memory device. The memory controller may include: a buffer block controller configured to control the memory device to store, in at least one of the main blocks, data stored in at least one of the buffer blocks; a mapping table manager configured to generate a P2P mapping table including mapping information between a buffer address that is a physical address of the at least one buffer block and a main address that is a physical address of the at least one main block; and a read operation controller configured to control, when a read request is received, the memory device to read the data based on the main address or the buffer address.

Abstract: A storage device includes a nonvolatile memory; a controller configured to control a write operation of the nonvolatile memory according to a write request received from a host and transmit a response to the write request to the host; and write buffers configured to store write data received with the write request. The controller is further configured to: set a response transmission delay time based on an available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time, transmit the response to the write request to the host after the response transmission delay time passes, and dynamically adjust, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller for controlling a plurality of memory devices in which data is stored may include a host interface configured to receive a request and a logical address corresponding to the request from a host, a processor including multiple cores, each configured to receive the logical address from the host interface and generate mapping information indicating a mapping relationship between the logical address and a physical address and a bitmap storage configured to store a bitmap indicating which core of the multiple cores each of previously-received logical addresses is assigned, wherein the host interface assigns the logical address to one of the multiple cores based on the bitmap.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including buffer blocks and main blocks, and a memory controller configured to control the memory device. The memory controller may include: a buffer block controller configured to control the memory device to store, in at least one of the main blocks, data stored in at least one of the buffer blocks; a mapping table manager configured to generate a P2P mapping table including mapping information between a buffer address that is a physical address of the at least one buffer block and a main address that is a physical address of the at least one main block; and a read operation controller configured to control, when a read request is received, the memory device to read the data based on the main address or the buffer address.

Abstract: A memory system includes a memory device configured to store data through a write operation and output the stored data as read data through a read operation; a buffer memory configured to store the read data output from the memory device; a controller configured to control the memory device such that the memory device performs the read operation in response to a read request received from a host, and to control the buffer memory to store the read data in the buffer memory. When the read request corresponds to an asynchronous read operation, the controller may allocate a partial area of the buffer memory as storage space for the read data after the read operation of the memory device is completed.