Patents by Inventor Seung On Kang

Seung On Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8040154
    Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: October 18, 2011
    Inventors: Lew Chua-Eoan, Matthew Nowak, Seung Kang
  • Publication number: 20110148669
    Abstract: Provided are a thimble-type intermediation device and a method for recognizing a finger gesture using the same. The thimble-type intermediation device includes: a motion sensing unit sensing a motion of a user's finger and generating the sensed result as motion data; a tactile sensing block sensing a tactile behavior of the user's finger and generating the sensed result as tactile data; a control unit recognizing the gesture and tactile behavior of the user's finger on the basis of the generated motion data and tactile data, and outputting the recognition result as recognition result information; and a wireless communication unit transmitting the recognition result information to a robot system.
    Type: Application
    Filed: July 28, 2010
    Publication date: June 23, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Seung KANG, Jae Hong Kim, Chan Kyu Park, Cheon Shu Park, Dae Ha Lee, Min Su Jang, Hyeon Sung Cho, Joo Chan Sohn, Jae Yeon Lee, Yun Koo Chung
  • Publication number: 20110144975
    Abstract: Disclosed is a typewriter system and a text input method capable of accurately recognizing words by correcting words input using a mediated interface device based on a dictionary. A plurality of texts are combined by referencing a text recognition order set in which recognition results of texts are arranged according to a recognition order from texts input through the mediated interface device and the combined text is filtered using part index maps formed of part words that are an accumulated set of texts forming complete words. The part words passing through the part index maps is again filtered using a dictionary including context information formed of a set of words in a specific category, thereby making it possible to accurately recognize the words. The part words that cannot form words in a dictionary are removed in advance using the part index maps, thereby improving the recognition efficiency.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 16, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Dae Ha LEE, Jae Hong KIM, Min Su JANG, Chan Kyu PARK, Hyeon Sung CHO, Sang Seung KANG, Cheon Shu PARK, Joo Chan SOHN, Jae Yeon LEE, Yun Koo CHUNG
  • Publication number: 20110051509
    Abstract: A system and method to manufacture magnetic random access memory is disclosed. In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer into a source line having a substantially rectilinear portion. The method also includes coupling the source line, at the substantially rectilinear portion, to a first transistor using a first via. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction device. The method includes coupling the source line to a second transistor using a second via, where the second transistor is configured to supply a second current received from the source line to a second magnetic tunnel junction device.
    Type: Application
    Filed: August 26, 2009
    Publication date: March 3, 2011
    Applicant: QUALCOMM Incorporated
    Inventors: Hari M. Rao, Seung Kang, Xiaochun Zhu, Sean Li, Ken Lee, Matthew M. Nowak, Robert J. Walden
  • Patent number: 7797079
    Abstract: An apparatus for controlling a robot and a method thereof are provided. The apparatus includes: a state interpretation unit determining whether or not a current situation belongs to a preset unstable state by evaluating the current situation based on a plurality of perception information items; and a target generation unit setting a target action of the robot by comparing the current situation and the determination result with a predetermined value system, and then, modifying the target action by receiving a feedback of the action performance result of the robot as perception information. According to the method and apparatus, by inputting a processing procedure and a value system to solve a variety of unstable states that can occur in situations of a user and circumstances surrounding the robot, the robot can actively respond with actions.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: September 14, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Min Su Jang, Joo Chan Sohn, Young Cheol Go, Sang Seung Kang, Young Jo Cho
  • Publication number: 20100216289
    Abstract: Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor pillars on a semiconductor substrate. The semiconductor substrate between the semiconductor pillars may be etched to form a trench region. A dielectric isolation pattern partially filling the trench region may be formed, and dielectric sidewall spacers may be formed on sidewalls of the semiconductor pillars. Metal-semiconductor compound regions may be formed on sidewalls of a portion of the trench region that is not filled by the isolation pattern.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 26, 2010
    Inventors: Jong-Chul Park, Yun-Seung Kang
  • Patent number: 7745290
    Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Seo, Jong-Heui Song, Jae-Seung Hwang, Min-Chul Chae, Woo-Jin Cho, Yun-Seung Kang, Young-Mi Lee
  • Patent number: 7728622
    Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 1, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Lew Chua-Eoan, Matthew Nowak, Seung Kang
  • Patent number: 7682450
    Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
  • Publication number: 20100065912
    Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Seung KANG, Eun-Kuk CHUNG, Joon KIM, Jin-Hong KIM, Suk-Chul BANG
  • Patent number: 7585757
    Abstract: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Seon Ahn, Joon Kim, Jin-Hong Kim, Suk-Chul Bang, Eun-Kuk Chung, Hyung-Mo Yang, Chang-Yeon Yoo, Yun-Seung Kang, Kyung-Tae Jang
  • Publication number: 20090153499
    Abstract: A system for recognizing a touch action that a person has performed upon an object, is provided with a sensor component for detecting a sensor value corresponding to the touch action through an inertial sensor attached to part of a body of the person; and a signal processing component for recognizing the touch action from the sensor value detected by the sensor component and transferring the recognized touch action to the object. Further, a method for recognizing a touch action that a person has performed upon an object, is provided with: detecting a sensor value corresponding to the touch action through an inertial sensor attached to part of a body of the person; and recognizing the touch action from the detected sensor value and transferring the recognized touch action to the object.
    Type: Application
    Filed: August 13, 2008
    Publication date: June 18, 2009
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae Hong KIM, Sang Seung Kang, Joo Chan Sohn, Hyun Kyu Cho, Young-Jo Cho
  • Patent number: 7531450
    Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Seung Kang, Jun Seo, Min-Chul Chae, Jae-Seung Hwang, Sung-Un Kwon, Woo-Jin Cho
  • Publication number: 20090099693
    Abstract: A system for control of emotional action expression including an emotion engine for creating an emotion according to information provided from a plurality of sensors, and an emotional action expression/actuation control unit for detecting an emotion platform profile and an emotion property from the created emotion and determining the action expression corresponding to the created emotion to control a target actuator. A control unit controls the motion of the target actuator under the control of the emotional action expression/actuation control unit.
    Type: Application
    Filed: September 10, 2008
    Publication date: April 16, 2009
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang Seung Kang, Jae Hong Kim, Joo Chan Sohn, Hyun Kyu Cho, Young Jo Cho
  • Publication number: 20080124871
    Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.
    Type: Application
    Filed: July 3, 2007
    Publication date: May 29, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun SEO, Jong-Heui SONG, Jae-Seung HWANG, Min-Chul CHAE, Woo-Jin CHO, Yun-Seung KANG, Young-Mi LEE
  • Publication number: 20080082209
    Abstract: A robot actuator and a robot actuating method. In the robot actuator, when an input part detects an external stimulus signal according to a user's contact, a control part receives the detected external stimulus signal to create sensor data. The control part determines an output reaction, and an output actuator through the created sensor data and controls the output actuator according to the determined output reaction. Thus, an axial skeletal unit of an output part is moved according to an operation of the output actuator to express the output reaction. Accordingly, a natural, lively reaction of the robot actuator to an external stimulus can be achieved.
    Type: Application
    Filed: September 26, 2007
    Publication date: April 3, 2008
    Inventors: Sang Seung KANG, Jae Hong KIM, Joo Chan SOHN, Young Jo CHO
  • Publication number: 20080026508
    Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.
    Type: Application
    Filed: October 8, 2007
    Publication date: January 31, 2008
    Applicant: Agere Systems Inc.
    Inventors: Vance Archer, Kouros Azimi, Daniel Chesire, Warren Gladden, Seung Kang, Taeho Kook, Sailesh Merchant, Vivian Ryan
  • Publication number: 20080007516
    Abstract: An electrophoretic display and a method of manufacturing the electrophoretic display are provided. The electrophoretic display includes an lower electrode formed on an under layer, an lower electrode protection layer formed on the lower electrode, an insulating template formed on the lower electrode protection layer and having a plurality of holes of smaller size than the wavelength of visible rays region, a dielectric fluid filling the holes and having a color, a plurality of charged particles suspended in the dielectric fluid filling each of the plurality of holes having a color different from the color of the dielectric fluid, and an upper electrode formed on the insulating template in sequential order. Accordingly, a problem of agglomeration of the charged particles can be solved by the insulating template having holes of smaller size than the wavelength of visible rays region, and thus a reliable electrophoretic display emitting light of one color or natural colors is achieved.
    Type: Application
    Filed: September 17, 2007
    Publication date: January 10, 2008
    Inventors: Seong Ahn, Kyung Suh, Seung Kang, Yong Lee, Chul Kim, Meyoung Joung, Mi Kim, Gun Lee
  • Publication number: 20070287287
    Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 13, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Seung KANG, Jun SEO, Min-Chul CHAE, Jae-Seung HWANG, Sung-Un KWON, Woo-Jin CHO
  • Publication number: 20070223561
    Abstract: Disclosed herein is a working electrode structure of a biosensor, in which the shape of one end of the working electrode including a reaction portion is modified to have different electrode widths for each section along a lengthwise direction within the reaction portion, so that although there is caused a length error in the reaction portion of the working electrode in the process of fixing a reagent during the fabrication of the electrode, an error for an area of the reaction portion can be restricted at the maximum, which results in a reduction in measurement error and an improvement in measurement reliability.
    Type: Application
    Filed: May 15, 2006
    Publication date: September 27, 2007
    Inventors: Yon Ahn, Jun Ryu, Seung Kang