Patents by Inventor Seung-pil Chung

Seung-pil Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259881
    Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk Kim, Dae Hyun Jang, Seung Pil Chung, Sung II Cho
  • Patent number: 10319864
    Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk Kim, Dae Hyun Jang, Seung Pil Chung, Sung Il Cho
  • Publication number: 20180374961
    Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.
    Type: Application
    Filed: December 20, 2017
    Publication date: December 27, 2018
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk KIM, Dae Hyun JANG, Seung Pil CHUNG, Sung Il CHO
  • Patent number: 9978756
    Abstract: Semiconductor chips are provided. A semiconductor chip includes a peripheral circuit region on a substrate. The semiconductor chip includes a semiconductor layer on the peripheral circuit region. The semiconductor chip includes a cell region on the semiconductor layer. Moreover, the semiconductor chip includes a layer/connector that is adjacent the semiconductor layer. Methods of manufacturing semiconductor chips are also provided.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyuk Kim, Seung-pil Chung, Jae-ho Min
  • Patent number: 9865540
    Abstract: A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyuk Kim, Jae-Ho Min, Jong-Kyoung Park, Seung-Pil Chung
  • Publication number: 20170330887
    Abstract: Semiconductor chips are provided. A semiconductor chip includes a peripheral circuit region on a substrate. The semiconductor chip includes a semiconductor layer on the peripheral circuit region. The semiconductor chip includes a cell region on the semiconductor layer. Moreover, the semiconductor chip includes a layer/connector that is adjacent the semiconductor layer. Methods of manufacturing semiconductor chips are also provided.
    Type: Application
    Filed: January 23, 2017
    Publication date: November 16, 2017
    Inventors: Hyuk Kim, Seung-pil Chung, Jae-ho Min
  • Patent number: 9806204
    Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Soo Ahn, O Ik Kwon, Bum-Soo Kim, Hyun-Sung Kim, Kyoung-Sub Shin, Min-Kyung Yun, Seung-Pil Chung, Won-Bong Jung
  • Publication number: 20170117222
    Abstract: A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.
    Type: Application
    Filed: July 12, 2016
    Publication date: April 27, 2017
    Inventors: Hyuk KIM, Jae-Ho MIN, Jong-Kyoung PARK, Seung-Pil CHUNG
  • Patent number: 9502427
    Abstract: A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: November 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jin Shin, Kyung-Hyun Kim, Jung-Hun No, Choong-Kee Seong, Seung-Pil Chung, Jung-Geun Jee
  • Publication number: 20160260726
    Abstract: A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.
    Type: Application
    Filed: February 19, 2016
    Publication date: September 8, 2016
    Inventors: Jae-Jin SHIN, Kyung-Hyun KIM, Jung-Hun NO, Choong-Kee SEONG, Seung-Pil CHUNG, Jung-Geun JEE
  • Publication number: 20150054054
    Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
    Type: Application
    Filed: November 7, 2014
    Publication date: February 26, 2015
    Inventors: Sung-Soo AHN, O Ik KWON, Bum-Soo KIM, Hyun-Sung KIM, Kyoung-Sub SHIN, Min-Kyung YUN, Seung-Pil CHUNG, Won-Bong JUNG
  • Patent number: 8883588
    Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo Ahn, O Ik Kwon, Bum-Soo Kim, Hyun-Sung Kim, Kyoung-Sub Shin, Min-Kyung Yun, Seung-Pil Chung, Won-Bong Jung
  • Patent number: 8765572
    Abstract: A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-lack Choi, Chang-hyun Cho, Seung-pil Chung, Hyun-seok Jang, Du-heon Song, Jung-dal Choi
  • Patent number: 8541306
    Abstract: A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Song-yi Yang, Seung-pil Chung, Dong-hyun Kim, O-ik Kwon, Hong Cho
  • Publication number: 20130134496
    Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
    Type: Application
    Filed: August 30, 2012
    Publication date: May 30, 2013
    Inventors: Sung-Soo AHN, O IK KWON, Bum-Soo KIM, Hyun-Sung KIM, Kyoung-Sub SHIN, Min-Kyung YUN, Seung-Pil CHUNG, Won-Bong JUNG
  • Patent number: 8361904
    Abstract: A semiconductor device and method are disclosed in which an interlayer insulating layer is patterned using multiple overlaying masks to define the geometry of contact plugs and corresponding wiring layers separated by fine pitches.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-seok Lee, Seung-pil Chung, Ji-young Lee
  • Patent number: 8258610
    Abstract: Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong Cho, Seung-Pil Chung, Dong-Seok Lee
  • Publication number: 20120049377
    Abstract: A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.
    Type: Application
    Filed: January 3, 2011
    Publication date: March 1, 2012
    Inventors: Song-Yi Yang, Seung-pil Chung, Dong-hyun Kim, O-ik Kwon, Hong Cho
  • Publication number: 20110318914
    Abstract: A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 29, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-lack Choi, Chang-hyun Cho, Seung-pil Chung, Hyun-seok Jang, Du-heon Song, Jung-dal Choi
  • Publication number: 20110127595
    Abstract: Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 2, 2011
    Inventors: Hong Cho, Seung-Pil Chung, Dong-Seok Lee