Abstract: A semiconductor device includes cell lower conductive lines and peripheral lower conductive lines on a substrate, lower electrode contacts on the cell lower conductive lines, peripheral conductive contacts on the peripheral lower conductive lines, variable resistance patterns horizontally spaced apart from each other on the lower electrode contacts. The lower electrode contacts are respectively connected to the variable resistance patterns. Peripheral conductive lines are horizontally spaced apart from the variable resistance patterns on the peripheral conductive contacts. The peripheral conductive contacts are connected to the peripheral conductive lines. The cell and peripheral lower conductive lines are connected to the lower electrode contacts and the peripheral conductive contacts, respectively. The cell and peripheral lower conductive lines are at the same height.

Abstract: A magnetic memory device includes first and second upper insulating layers and a first mold layer sequentially stacked on a first substrate region; a first primary and first secondary wiring structure spaced apart in a first direction in the first upper insulating layer; a second wiring structure on the first primary wiring structure and a reference wiring structure on the first secondary wiring structure, in the second upper insulating layer; a first structure on the second wiring structure; a second structure on the reference wiring structure; a lower electrode contact between the second wiring structure and the first structure, and not between the reference wiring structure and the second structure, in the first mold layer; a bit line structure on the first structure; and a reference bit line structure on the second structure. The first and second structure include a lower electrode, MTJ structure, intermediate electrode, and upper electrode.

Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.

Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.

Abstract: A magnetic memory device may include a substrate including a first region and a second region, a first interlayer insulating layer on the substrate, a first capping layer on the first interlayer insulating layer, the first capping layer covering the first and second regions of the substrate, a second interlayer insulating layer on a portion of the first capping layer covering the first region of the substrate, a bottom electrode contact included in the second interlayer insulating layer, a magnetic tunnel junction pattern on the bottom electrode contact, and a second capping layer on the second interlayer insulating layer, the second capping layer being in contact with the first capping layer on the second region of the substrate.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.

Abstract: A method of fabricating a semiconductor device includes forming a magnetic tunnel junction layer including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer interposed between the first and second magnetic layers, patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern, forming an insulating layer to cover the magnetic tunnel junction pattern, and performing a thermal treatment process to crystallize at least a portion of the first and second magnetic layers. The thermal treatment process may include performing a first thermal treatment process at a first temperature, after the forming of the magnetic tunnel junction layer, and performing a second thermal treatment process at a second temperature, which is higher than or equal to the first temperature, after the forming of the insulating layer.

Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Abstract: A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.

Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.

Abstract: A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.

Abstract: An MRAM device comprises an insulating interlayer comprising a flat first upper surface on a first region and a second region of a substrate. A pattern structure comprising pillar-shaped magnetic tunnel junction (MTJ) structures and a filling layer pattern between the MTJ structures is formed on the insulating interlayer of the first region. The pattern structure comprises a flat second upper surface that is higher than the first upper surface. Bit lines are formed on the pattern structure that contact top surfaces of the MTJ structures. An etch-stop layer is formed on the pattern structure between the bit lines of the first region and the first upper surface of the first insulating interlayer of the second region. A first portion of an upper surface of the etch-stop layer on the first region is higher than a second portion of the upper surface of the etch-stop layer on the second region.