Abstract: A self-circularization RNA construct that can be expressed in a DNA vector and simultaneously circularized through a self-targeting and splicing reaction to form a circRNA is disclosed. The circRNA can consist only of a gene of interest which can be a coding, non-coding, or a combination thereof. The gene of interest has the advantage of being able to rapidly express a peptide or protein. The formed circRNA has a circular structure and has a stable and high half-life because 5? and 3? ends are not exposed. Accordingly, functional RNA such as miRNA, anti-miRNA, siRNA, shRNA, aptamer, functional RNA for gene/RNA editing, ADAR (adenosine deaminase acting on the RNA)-recruiting RNA, mRNA vaccine, mRNA therapeutic agent, vaccine adjuvant, and CAR-T mRNA can be produced as a stable circRNA in cells.

Abstract: A rotational deck which is used for an emergency vehicle return apparatus in a section of a median strip of a road, includes a pair of angle decks configured to be folded up to serve as the median strip in a normal state, and be unfolded down by hydraulic cylinders toward a surface of the road to serve as a vehicle pass in an event of emergency, and a front block part coupled, by a link unit, to a lower portion of each angle deck. The front block part includes a front block having a shape to reduce a shock from a collision, one or more front block frames configured to provide rigidity by supporting a rear surface of the front block, and a bottom frame configured to support the front block and a lower portion of the front block frame.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Abstract: Disclosed is a rotational deck with a shock-reducing front block of an emergency vehicle return apparatus for a median strip, which constitutes the emergency vehicle return apparatus installed for each section of a median strip (100) of a road, the rotational deck including: a front block part (2) fastened, by a link unit (3), to a lower portion of each of a pair of symmetrically installed angle decks (12) of a rotational deck (1) configured such that the pair of angle decks (12) is rotated by hydraulic cylinders (14), respectively, and adjoins left and right paved surfaces of the road in the event of emergency, in which the front block part has a structure that serves as the median strip at normal times when the rotational deck does not operate, and reduces impact when a vehicle collides with the front block part.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; an active pattern spaced apart from the substrate and extending in a first direction; and a gate structure on the active pattern and extending in a second direction crossing the first direction, wherein a lower portion of the active pattern extends in the first direction and includes a first lower surface that is sloped with respect to an upper surface of the substrate.

Abstract: A semiconductor device has a fin-type structure which extends in a first direction and includes a laminate of oxide and semiconductor patterns disposed one on another on a first region of a substrate, and a first gate electrode that extends longitudinally in a second direction different from the first direction on the fin-type structure. Each oxide pattern is an oxidized compound containing a first element.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; an active pattern spaced apart from the substrate and extending in a first direction; and a gate structure on the active pattern and extending in a second direction crossing the first direction, wherein a lower portion of the active pattern extends in the first direction and includes a first lower surface that is sloped with respect to an upper surface of the substrate.

Abstract: A semiconductor single crystal structure may include a substrate; a defect trapping stack disposed on the substrate; and a semiconductor single crystal disposed on the defect trapping stack, and having a lattice mismatch with a crystal of the substrate, in which the defect trapping stack may include a first dielectric layer disposed on the substrate, and having at least one first opening, a second dielectric layer disposed on the first dielectric layer, and having at least one second opening, a third dielectric layer disposed on the second dielectric layer, and having at least one third opening, and a fourth dielectric layer disposed on the third dielectric layer, and having at least one fourth opening, and in which the semiconductor single crystal may extend to a region of the substrate defined in the at least one first opening through the at least one first to fourth opening.

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

Abstract: The semiconductor device includes a first multi-channel active pattern protruding from a substrate, and having a first height, a second multi-channel active pattern on the substrate, being spaced apart from the substrate, and having a second height that is less than the first height, and a gate electrode on the substrate, intersecting the first multi-channel active pattern and the second multi-channel active pattern.

Abstract: A semiconductor device has a fin-type structure which extends in a first direction and includes a laminate of oxide and semiconductor patterns disposed one on another on a first region of a substrate, and a first gate electrode that extends longitudinally in a second direction different from the first direction on the fin-type structure. Each oxide pattern is an oxidized compound containing a first element.

Abstract: A semiconductor single crystal structure may include a substrate; a defect trapping stack disposed on the substrate; and a semiconductor single crystal disposed on the defect trapping stack, and having a lattice mismatch with a crystal of the substrate, in which the defect trapping stack may include a first dielectric layer disposed on the substrate, and having at least one first opening, a second dielectric layer disposed on the first dielectric layer, and having at least one second opening, a third dielectric layer disposed on the second dielectric layer, and having at least one third opening, and a fourth dielectric layer disposed on the third dielectric layer, and having at least one fourth opening, and in which the semiconductor single crystal may extend to a region of the substrate defined in the at least one first opening through the at least one first to fourth opening.

Abstract: In one embodiment, the memory element may include a first electrode, a second electrode spaced apart from the first electrode, a memory layer between the first electrode and the second electrode, and an auxiliary layer between the memory layer and the second electrode. The auxiliary layer provides a multi-bit memory characteristic to the memory layer.

Abstract: A resistive memory device includes: a first electrode; a variable resistive material layer that is formed on the first electrode and includes a metal oxide NxMOy (wherein 0.001<x<0.30 and 0.5<y<2.5) doped with nitrogen; and a second electrode that is formed on the variable resistive material layer. The variable resistive material layer has a multibit memory characteristic.

Abstract: A memory device may include a first electrode and a second electrode spaced apart from the first electrode. The memory device may further include a memory element disposed between the first electrode and the second electrode and a switching element disposed between the first electrode and the second electrode. The switching element may be configured to control signal access to the memory element. The memory device may further include a barrier layer disposed between the memory element and the switching element, the barrier layer including an insulation material.