Patents by Inventor Seung-Seok PYO

Seung-Seok PYO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240347002
    Abstract: A display device includes a plurality of first pixels disposed in a first pixel area and initialized by a voltage of a first initialization power source, a plurality of second pixels disposed in a second pixel area and initialized by a voltage of a second initialization power source different from the first initialization power source, a data driver that supplies a data signal to a plurality of data lines connected to the first pixels and the second pixels, and a scan driver that supplies a scan signal to a plurality of scan lines connected to the first pixels and the second pixels. A black data signal supplied from the data driver to the first pixels and a black data signal supplied from the data driver to the second pixels are set to the same voltage.
    Type: Application
    Filed: December 29, 2023
    Publication date: October 17, 2024
    Inventors: Si Beak PYO, Seung Kyu LEE, Ji Hye MOON, Young Kyo SEO, Sung Jin KIM, Hyun Seok HONG
  • Patent number: 8975132
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Bong-Ho Choi, Jin-Yul Lee, Seung-Seok Pyo
  • Patent number: 8941157
    Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Seong-Su Lim, Sung-Eun Park, Seung-Seok Pyo, Min-Cheol Kang
  • Publication number: 20140302663
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 9, 2014
    Inventors: Hyung-Hwan KIM, Bong-Ho CHOI, Jin-Yul LEE, Seung-Seok PYO
  • Publication number: 20140217545
    Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.
    Type: Application
    Filed: April 11, 2014
    Publication date: August 7, 2014
    Applicant: SK hynix Inc.
    Inventors: Hyung-Hwan KIM, Seong-Su LIM, Sung-Eun PARK, Seung-Seok PYO, Min-Cheol KANG
  • Patent number: 8786047
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: July 22, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Bong-Ho Choi, Jin-Yul Lee, Seung-Seok Pyo
  • Patent number: 8697525
    Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Seong-Su Lim, Sung-Eun Park, Seung-Seok Pyo, Min-Cheol Kang
  • Publication number: 20130249048
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Application
    Filed: July 9, 2012
    Publication date: September 26, 2013
    Inventors: Hyung-Hwan KIM, Bong-Ho CHOI, Jin-Yul LEE, Seung-Seok PYO
  • Publication number: 20120168899
    Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.
    Type: Application
    Filed: May 5, 2011
    Publication date: July 5, 2012
    Inventors: Hyung-Hwan KIM, Seong-Su Lim, Sung-Eun Park, Seung-Seok Pyo, Min-Cheol Kang
  • Publication number: 20120149202
    Abstract: A method for fabricating a semiconductor device includes forming a trench by etching a substrate using a hard mask layer as an etch barrier, forming an insulation material which covers sidewalls of the trench, forming a sacrificial material which fills the trench and is planarized to expose the surface of the hard mask layer, forming a masking layer having a damaged region over the sacrificial material, selectively removing the damaged region of the masking layer, exposing a portion of the insulation material, which is formed at a sidewall of the trench, by etching a portion of the sacrificial material using the remaining masking layer as a barrier, and forming a side contact by removing the exposed insulation material.
    Type: Application
    Filed: December 29, 2010
    Publication date: June 14, 2012
    Inventor: Seung-Seok PYO