Patents by Inventor Seung Soo Kim
Seung Soo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250117161Abstract: Provided herein is a method of operating a host device. The method may include, a determining that read requests for data in a first file are successive, in response to the determination that read requests are successive, generating a first read command that instructs second data to be read ahead, the second data being successive to first data, determining a logical address corresponding to the first read command, providing to a storage device the first read command and the logical address, determining whether a read-ahead request for the first file has been completed, based on a first file pointer and a first offset corresponding to a storage area within the storage device in which the first file is stored, and executing a read-ahead request for a second file in response to the determination that the read-ahead request for the first file has been completed.Type: ApplicationFiled: February 26, 2024Publication date: April 10, 2025Inventors: Chi Je PARK, Seung Soo KIM, Hyeong Jae CHOI
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Publication number: 20240403206Abstract: The present disclosure relates to a storage device capable of receiving early suspend information from an external device (e.g., host) and performing an appropriate operation during a power saving mode for an application installed on the external device, and a method of operating a memory controller of the storage device. The method of operating a memory controller may include: receiving early suspend information from an external device; and controlling a background operation according to the reception of the early suspend information. The background operation refers to an operation that is performed internally regardless of a request from the external device.Type: ApplicationFiled: October 24, 2023Publication date: December 5, 2024Inventors: Hyeong Jae CHOI, Seung Soo KIM, Chi Je PARK
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Publication number: 20240338136Abstract: A storage device may receive a write command which requests to write target data and includes an identifier for the target data, a size of the target data, and a flag indicating that the target data is cold data. The storage device may write the target data to one or more consecutive target memory blocks among the plurality of memory blocks.Type: ApplicationFiled: August 17, 2023Publication date: October 10, 2024Inventors: Seung Soo KIM, Hyeong Jae CHOI
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Publication number: 20240266930Abstract: The apparatus for manufacturing a laminated core with heating adhesion according to the present invention is characterized by comprising a lower die 10 comprising a plurality of piercing dies 11, an adhesive applying unit 12 installed on one side of the piercing dies 11, and a laminating unit 13 installed on one side of the adhesive applying unit 12; an upper die 20 comprising piercing punches 21 arranged above the piercing dies 11 and a blanking punch 22 arranged above the laminating unit 13; and an SB steel strip 102 continuously fed to an upper part of the lower die 10, for being formed into a laminar member 101 by operation of the piercing punch 21 and the blanking punch 22, wherein the laminating unit 13 comprises a blanking die 131, a squeeze ring 132 installed at a lower part of the blanking die 131, and a first heating unit 135 installed at a lower part of the squeeze ring 132, and laminates the laminar member 101 in the inner diameter surface of the squeeze ring 132 to manufacture a laminated core 10Type: ApplicationFiled: November 26, 2021Publication date: August 8, 2024Applicant: BMC CO., LTD.Inventor: Seung Soo KIM
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Publication number: 20240266929Abstract: The apparatus for manufacturing a laminated core according to the present invention is characterized by comprising a lower die 10 comprising a plurality of piercing dies 11 and a laminating unit 13; and an upper die 20 comprising piercing punches 21 arranged above the piercing dies 11 and a blanking punch 22 arranged above the laminating unit 13, the laminating unit 13 comprising a blanking die 131 and a squeeze ring 132 installed at a lower part of the blanking die 131, the apparatus further comprising a back pressure unit 14 installed at a lower part of the squeeze ring 132, wherein the back pressure unit 14 comprises a back pressure plate 141; a back pressure cylinder 142 for operating a cylinder rod 143 which moves 144 the back pressure plate 141 up and down; and a scale bar head 145 installed at a lower part of the cylinder rod 143.Type: ApplicationFiled: November 26, 2021Publication date: August 8, 2024Applicant: BMC CO., LTD.Inventor: Seung Soo KIM
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Patent number: 10056339Abstract: A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer is on the substrate and includes a pad region and a peripheral region adjacent to the pad region. The data storage elements are on the pad region of the first insulation layer. The contact plug penetrates the first insulation layer on the peripheral region. The first dummy dam penetrates the first insulation layer and is disposed between the data storage elements and the contact plug.Type: GrantFiled: June 20, 2017Date of Patent: August 21, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeon-Woo Jang, Junghwan Park, Ramakanth Kappaganthu, Sungjin Kim, Junyong Noh, Jung-Hoon Han, Seung Soo Kim, Sungjin Kim, Sojung Lee
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Publication number: 20180040571Abstract: A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer is on the substrate and includes a pad region and a peripheral region adjacent to the pad region. The data storage elements are on the pad region of the first insulation layer. The contact plug penetrates the first insulation layer on the peripheral region. The first dummy dam penetrates the first insulation layer and is disposed between the data storage elements and the contact plug.Type: ApplicationFiled: June 20, 2017Publication date: February 8, 2018Inventors: HYEON-WOO JANG, JUNGHWAN PARK, RAMAKANTH KAPPAGANTHU, SUNGJIN KIM, JUNYONG NOH, JUNG-HOON HAN, SEUNG SOO KIM, SUNGJIN KIM, SOJUNG LEE
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Patent number: 7683682Abstract: A frequency divider for a wireless communication system is provided. A frequency divider includes a body bias voltage generator and a divider. The body bias voltage generator generates a body bias voltage including a PMOS body bias voltage and an NMOS body bias voltage whose voltage levels are controlled according to an input signal. The divider includes a plurality of flip-flops whose operation points are determined according to the body bias voltage, and generates an output signal by dividing a frequency of the input signal by N. Each of the flip-flops may include a PMOS logic and an NMOS logic. The PMOS logic may include a plurality of PMOS transistors whose operation points are determined according to the PMOS body bias voltage. The NMOS logic may be connected electrically to the PMOS logic and include a plurality of NMOS transistors whose operation points are determined according to the NMOS body bias voltage.Type: GrantFiled: August 28, 2008Date of Patent: March 23, 2010Assignee: Korea Electronics Technology InstituteInventors: Kwang Ho Won, Yeon Kug Moon, Hyun Chol Shin, Seung Soo Kim
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Publication number: 20100052738Abstract: A frequency divider for a wireless communication system is provided. A frequency divider includes a body bias voltage generator and a divider. The body bias voltage generator generates a body bias voltage including a PMOS body bias voltage and an NMOS body bias voltage whose voltage levels are controlled according to an input signal. The divider includes a plurality of flip-flops whose operation points are determined according to the body bias voltage, and generates an output signal by dividing a frequency of the input signal by N. Each of the flip-flops may include a PMOS logic and an NMOS logic. The PMOS logic may include a plurality of PMOS transistors whose operation points are determined according to the PMOS body bias voltage. The NMOS logic may be connected electrically to the PMOS logic and include a plurality of NMOS transistors whose operation points are determined according to the NMOS body bias voltage.Type: ApplicationFiled: August 28, 2008Publication date: March 4, 2010Inventors: Kwang Ho Won, Yeon Kug Moon, Hyun Chol Shin, Seung Soo Kim
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Patent number: 7659185Abstract: Disclosed are a method for forming a silicon thin-film on a substrate, and more particularly a method for forming a polycrystalline silicon thin-film of good quality on a flexible metal substrate. A metal substrate (110) is prepared and a surface of the metal substrate (110) is flattened. An insulation film (120) is formed on the metal substrate (110). An amorphous silicon layer (130) is formed on the insulation film (120). A metal layer (140) is formed on the amorphous silicon layer (130). A sample on the metal substrate (110) is heated and crystallized.Type: GrantFiled: September 2, 2004Date of Patent: February 9, 2010Assignee: Kyunghee University Industrial & Academic Collaboration FoundationInventors: Jin Jang, Jong-Hyun Choi, Seung-Soo Kim, Jae-Hwan Oh, Jun-Hyuk Chon
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Patent number: 7290338Abstract: Disclosed are an electric pole manufacturing apparatus having an improved distal end, capable of reducing the cost, arranging tensile cores corresponding to a design load, and providing a high quality electric pole, and a method of manufacturing the electric pole.Type: GrantFiled: March 13, 2003Date of Patent: November 6, 2007Assignee: Hammtek Asia, Inc.Inventors: Seung Soo Kim, Jung Ho Kong
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Publication number: 20060286780Abstract: Disclosed are a method for forming a silicon thin-film on a substrate, and more particularly a method for forming a polycrystalline silicon thin-film of good quality on a flexible metal substrate. A metal substrate (110) is prepared and a surface of the metal substrate (110) is flattened. An insulation film (120) formed on the metal substrate (110). An amorphous silicon layer (130) is formed on the insulation film (120). A metal layer (140) is formed on the amorphous silicon layer (130). A sample on the metal substrate (110) is heated and crystallized.Type: ApplicationFiled: September 2, 2004Publication date: December 21, 2006Inventors: Jin Jang, Jong-Hyun Choi, Seung-Soo Kim, Jae-Hwan Oh, Jun-Hyuk Chon
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Publication number: 20050032626Abstract: A method of catalysts reduction using non-thermal plasma according to the present invention is characterized to reduce catalysts containing metal compounds by bringing them into contact with hydrogen-containing gas under a non-thermal plasma state. In the method of catalysts reduction using non-thermal plasma according to the present invention, said non-thermal plasma is generated by dielectric barrier discharge. In the method of catalysts reduction using non-thermal plasma according to the present invention, the plasma energy that is required to vary depending on the types of metals is regulated by the magnitude of power via voltage regulation. In the method of catalysts reduction using non-thermal plasma according to the present invention, said reduction method is conducted in conjunction with existing methods of gaseous hydrogen reduction by heating, electrochemical reduction methods, or methods of reduction by adding organic or inorganic reducing agents.Type: ApplicationFiled: December 29, 2003Publication date: February 10, 2005Applicant: Korea Institute of Science and TechnologyInventors: Hyung Song, Hwaung Lee, Jae-Wook Choi, Gi-Seok Yang, Seung-Soo Kim, Byung-Ki Na