Abstract: A semiconductor package includes a semiconductor chip having bonding pads formed on a top surface and a first via hole and a second via hole formed on both-side edges; a passive element formed within the first via hole; a via wiring formed within the second via hole; a first wiring connected to the bonding pad at one end and connected to the passive element and the via wiring on a top surface of the semiconductor chip; a second wiring formed on a back surface of the semiconductor chip and formed to connect with the passive element and the via wiring; a first passivation film formed in such a way to expose one portion of the first wiring on a top surface of the semiconductor chip; and a second passivation film formed in such a way to expose one portion of the second wiring on a bottom surface of the semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip having a first region and a second region. Bonding pads are formed and through-holes are defined in the first and second regions. Insulation layers are formed on sidewalls of the through-holes, and through-electrodes formed in the through-holes and connected with corresponding bonding pads. The insulation layers formed in the first and second regions have different thicknesses or dielectric constants.

Abstract: The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding pad group. In the present invention pad parts can be formed on the outside of the semiconductor chip module to conform with the standards of JEDEC. These pad parts are then connected to the semiconductor chips bonding pads through re-distribution layers. The pad parts of the semiconductor package can then conform to the JEDEC standards even while having a semiconductor chip with bonding pads smaller than the standards.

Abstract: The semiconductor package includes a plate having first via patterns formed on a center portion and second via patterns formed on edge portions; a connection wiring formed on a top surface of the plate to connect at least one first via patterns to at least one second via patterns; a plurality of passive elements formed on the top surface of the plate having a connection wiring formed thereon; a semiconductor chip having a plurality of bonding pads attached to a bottom surface of the plate and electrically connected to the first via patterns; and a plurality of external connection terminals each of which being attached to each of the second via pattern on the bottom surface of the plate.

Abstract: A semiconductor package capable of being efficiently stacked and a method of manufacturing the same is presented. The semiconductor package includes a semiconductor chip, an insulation layer, and a through-electrode. The semiconductor chip has a first surface and a second surface, a circuit section in the semiconductor chip, an internal circuit pattern electrically connected to the circuit section, and a through-hole that passes through the internal circuit pattern and through the first and second surfaces. The insulation layer is on a through-hole of the semiconductor chip and has an opening which exposes the internal circuit pattern which was exposed by the through-hole. The through-electrode is in the through-hole and electrically coupled to the internal circuit pattern which is exposed through the opening of the insulation layer.

Abstract: A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the to first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal.

Abstract: A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal.

Abstract: A semiconductor package includes a semiconductor chip having a first region and a second region. Bonding pads are formed and through-holes are defined in the first and second regions. Insulation layers are formed on sidewalls of the through-holes, and through-electrodes formed in the through-holes and connected with corresponding bonding pads. The insulation layers formed in the first and second regions have different thicknesses or dielectric constants.

Abstract: An image sensor module includes a transparent substrate having recesses defined in a lower face thereof. A light concentration member includes transparent light concentration parts each of which are disposed in a corresponding one of the recesses. Color filters are disposed over each of the light concentration parts and photo diode units having photo diodes are disposed over each of the color filters. An insulation member covers the photo diode units and input/output terminals disposed over the insulation member are each electrically connected to a corresponding photo diode unit.

Abstract: A semiconductor package includes a base substrate on which a semiconductor chip is placed so that a first surface thereof faces the base substrate. A circuit section is formed adjacent to the first surface. An insulation layer is formed on a second surface of the semiconductor chip which faces away from the first surface. Passive elements are formed on the insulation layer. Via patterns are formed to pass through the insulation layer and are connected to the passive elements. Via wirings are formed to pass through the semiconductor chip and connected to the circuit section, the via patterns and the base substrate. Outside connection terminals are attached to a first surface of the base substrate, which face away from a second surface of the base substrate on which the semiconductor chip is placed.

Abstract: A wafer level package including a semiconductor chip having a plurality of bonding pads on a front surface thereof; a lower insulation layer formed on the semiconductor chip to expose the bonding pads; re-distribution lines formed on the lower insulation layer to be connected to the bonding pads at first ends thereof; an upper insulation layer formed on the lower insulation layer including the re-distribution lines, with portions of the re-distribution lines exposed; solder balls attached to the exposed portions of the re-distribution lines; and a cap covering a rear surface of the semiconductor chip.

Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

Abstract: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Abstract: A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals.

Abstract: A method for fabricating a semiconductor package includes the steps of: forming a material layer containing conductive particles on a semiconductor chip having a plurality of bonding pads on the upper surface thereof, baking the material layers to a non-flowing state; attaching the semiconductor chip in a face down manner to a substrate having connecting pads on the location corresponding to the bonding pads by using the material layers containing conductive particles; applying voltage for a electrical signal exchange to the semiconductor chip and the substrate so that the conductive particles are gathered between the bonding pads of the semiconductor chip and the connecting pads of the substrate; and curing the conductive particles of the material layers so that the conductive particles gathered between the bonding pads of the semiconductor chip and the connecting pads of the substrate to an non-flowing state.

Abstract: The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding pad group. In the present invention pad parts can be formed on the outside of the semiconductor chip module to conform with the standards of JEDEC. These pad parts are then connected to the semiconductor chips bonding pads through re-distribution layers. The pad parts of the semiconductor package can then conform to the JEDEC standards even while having a semiconductor chip with bonding pads smaller than the standards.

Abstract: A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal.

Abstract: A semiconductor package includes a semiconductor chip having bonding pads formed on a top surface and a first via hole and a second via hole formed on both-side edges; a passive element formed within the first via hole; a via wiring formed within the second via hole; a first wiring connected to the bonding pad at one end and connected to the passive element and the via wiring on a top surface of the semiconductor chip; a second wiring formed on a back surface of the semiconductor chip and formed to connect with the passive element and the via wiring; a first passivation film formed in such a way to expose one portion of the first wiring on a top surface of the semiconductor chip; and a second passivation film formed in such a way to expose one portion of the second wiring on a bottom surface of the semiconductor chip.