Patents by Inventor Seunguk Han
Seunguk Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240290983Abstract: Provided are a negative electrode and a lithium battery including the same, the negative electrode including: a negative electrode current collector; and a negative electrode active material layer arranged on the negative electrode current collector. The negative electrode active material layer comprises a negative electrode active material and a composite conductive material, wherein the composite conductive material comprises a core and a coating layer, the core comprises a carbon-based conductive material, and the coating layer comprises an ion-conductive polymer.Type: ApplicationFiled: December 3, 2021Publication date: August 29, 2024Inventors: Junghyun Choi, Seunguk Kwon, Yeongap Kim, Kyoseon Koo, Kijun Kim, Ho Kim, Yuuya ARIKAWA, Seongho Jeon, Sungsoo Han
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Publication number: 20240071771Abstract: A method of manufacturing an integrated circuit device includes preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.Type: ApplicationFiled: July 20, 2023Publication date: February 29, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Youngwoo KIM, Yonghan PARK, Jiho PARK, Geumjung SEONG, Seunguk HAN
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Patent number: 11908797Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.Type: GrantFiled: December 21, 2020Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jiyoung Ahn, Seunguk Han, Sunghwan Kim, Seoryong Park, Kiseok Lee, Yoonyoung Choi, Taehee Han, Jiseok Hong
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Publication number: 20230411157Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer, a first separation layer, a first mandrel layer, a second separation layer and a second mandrel layer on a substrate; patterning the second mandrel layer to form second mandrel patterns; forming first spacers on the second mandrel patterns; removing the second mandrel patterns; patterning the second separation layer and the first mandrel layer to form first structures; forming a second spacer layer on the first structures and the first separation layer; anisotropically etching the second spacer layer to form second spacers on the first structures, and to form first dummy patterns and align key patterns on the first structures; and spin-coating a spin-on hard mask layer on the first separation layer, wherein the spin-on hard mask layer covers the first structures, the first dummy patterns and the align key patterns.Type: ApplicationFiled: April 19, 2023Publication date: December 21, 2023Inventors: Seungkyo Lee, Jongin Kang, Gyeyoung Kim, Youngwoo Kim, Yonghan Park, Woojin Jung, Seunguk Han, Juyoung Huh
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Publication number: 20230232616Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiseok HONG, Sangho Lee, Seoryong Park, Jiyoung Ahn, Kiseok Lee, Kiseok Lee, Yoonyoung Choi, Seunguk Han
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Patent number: 11690213Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.Type: GrantFiled: March 12, 2021Date of Patent: June 27, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Dongkyun Lim, Youngsin Kim, Kijin Park, Hoju Song, Dongkwan Yang, Sangho Yun, Gyuhyun Lee, Jieun Lee, Seunguk Han, Yoongi Hong
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Patent number: 11647627Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.Type: GrantFiled: February 5, 2021Date of Patent: May 9, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiseok Hong, Sangho Lee, Seoryong Park, Jiyoung Ahn, Kiseok Lee, Kiseok Lee, Yoonyoung Choi, Seunguk Han
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Patent number: 11557596Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.Type: GrantFiled: March 4, 2021Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seoryong Park, Seunguk Han, Jiyoung Ahn, Kiseok Lee, Yoonyoung Choi, Jiseok Hong
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Publication number: 20220077152Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.Type: ApplicationFiled: March 12, 2021Publication date: March 10, 2022Inventors: Dongkyun Lim, Youngsin Kim, Kijin Park, Hoju Song, Dongkwan Yang, Sangho Yun, Gyuhyun Lee, Jieun Lee, Seunguk Han, Yoongi Hong
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Publication number: 20220020758Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.Type: ApplicationFiled: March 4, 2021Publication date: January 20, 2022Inventors: SEORYONG PARK, SEUNGUK HAN, Jiyoung AHN, Kiseok LEE, YOONYOUNG CHOI, JISEOK HONG
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Publication number: 20210398569Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.Type: ApplicationFiled: February 5, 2021Publication date: December 23, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiseok Hong, Sangho Lee, Seoryong Park, Jiyoung Ahn, Kiseok Lee, Kiseok Lee, Yoonyoung Choi, Seunguk Han
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Publication number: 20210391259Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.Type: ApplicationFiled: December 21, 2020Publication date: December 16, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiyoung Ahn, Seunguk Han, Sunghwan Kim, Seoryong Park, Kiseok Lee, Yoonyoung Choi, Taehee Han, Jiseok Hong
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Patent number: 8953356Abstract: A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions.Type: GrantFiled: June 18, 2012Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Seunguk Han, Jay-Bok Choi, Dong-Hyun Lee, Namho Jeon
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Patent number: 8901646Abstract: A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region.Type: GrantFiled: December 27, 2012Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Namho Jeon, Min-chul Park, Seunguk Han
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Patent number: 8809930Abstract: Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.Type: GrantFiled: January 16, 2013Date of Patent: August 19, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Namho Jeon, Jun-Su Kim, Satoru Yamada, Jaehoon Lee, Seunguk Han, Jiyoung Kim, Jin-Seong Lee
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Publication number: 20130256774Abstract: Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.Type: ApplicationFiled: January 16, 2013Publication date: October 3, 2013Inventors: Namho JEON, Jun-Su KIM, Satoru YAMADA, Jaehoon LEE, Seunguk HAN, Jiyoung KIM, Jin-Seong LEE
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Patent number: 8368169Abstract: An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer.Type: GrantFiled: October 4, 2010Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seunguk Han, Satoru Yamada, Young Jin Choi
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Publication number: 20120320655Abstract: A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions.Type: ApplicationFiled: June 18, 2012Publication date: December 20, 2012Inventors: Seunguk Han, Jay-Bok Choi, Dong-Hyun Lee, Namho Jeon
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Publication number: 20110108962Abstract: An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer.Type: ApplicationFiled: October 4, 2010Publication date: May 12, 2011Inventors: Seunguk Han, Satoru Yamada, Young Jin Choi