Patents by Inventor Seunguk Han

Seunguk Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240290983
    Abstract: Provided are a negative electrode and a lithium battery including the same, the negative electrode including: a negative electrode current collector; and a negative electrode active material layer arranged on the negative electrode current collector. The negative electrode active material layer comprises a negative electrode active material and a composite conductive material, wherein the composite conductive material comprises a core and a coating layer, the core comprises a carbon-based conductive material, and the coating layer comprises an ion-conductive polymer.
    Type: Application
    Filed: December 3, 2021
    Publication date: August 29, 2024
    Inventors: Junghyun Choi, Seunguk Kwon, Yeongap Kim, Kyoseon Koo, Kijun Kim, Ho Kim, Yuuya ARIKAWA, Seongho Jeon, Sungsoo Han
  • Publication number: 20240071771
    Abstract: A method of manufacturing an integrated circuit device includes preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.
    Type: Application
    Filed: July 20, 2023
    Publication date: February 29, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Youngwoo KIM, Yonghan PARK, Jiho PARK, Geumjung SEONG, Seunguk HAN
  • Patent number: 11908797
    Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jiyoung Ahn, Seunguk Han, Sunghwan Kim, Seoryong Park, Kiseok Lee, Yoonyoung Choi, Taehee Han, Jiseok Hong
  • Publication number: 20230411157
    Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer, a first separation layer, a first mandrel layer, a second separation layer and a second mandrel layer on a substrate; patterning the second mandrel layer to form second mandrel patterns; forming first spacers on the second mandrel patterns; removing the second mandrel patterns; patterning the second separation layer and the first mandrel layer to form first structures; forming a second spacer layer on the first structures and the first separation layer; anisotropically etching the second spacer layer to form second spacers on the first structures, and to form first dummy patterns and align key patterns on the first structures; and spin-coating a spin-on hard mask layer on the first separation layer, wherein the spin-on hard mask layer covers the first structures, the first dummy patterns and the align key patterns.
    Type: Application
    Filed: April 19, 2023
    Publication date: December 21, 2023
    Inventors: Seungkyo Lee, Jongin Kang, Gyeyoung Kim, Youngwoo Kim, Yonghan Park, Woojin Jung, Seunguk Han, Juyoung Huh
  • Publication number: 20230232616
    Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiseok HONG, Sangho Lee, Seoryong Park, Jiyoung Ahn, Kiseok Lee, Kiseok Lee, Yoonyoung Choi, Seunguk Han
  • Patent number: 11690213
    Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 27, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongkyun Lim, Youngsin Kim, Kijin Park, Hoju Song, Dongkwan Yang, Sangho Yun, Gyuhyun Lee, Jieun Lee, Seunguk Han, Yoongi Hong
  • Patent number: 11647627
    Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiseok Hong, Sangho Lee, Seoryong Park, Jiyoung Ahn, Kiseok Lee, Kiseok Lee, Yoonyoung Choi, Seunguk Han
  • Patent number: 11557596
    Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seoryong Park, Seunguk Han, Jiyoung Ahn, Kiseok Lee, Yoonyoung Choi, Jiseok Hong
  • Publication number: 20220077152
    Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.
    Type: Application
    Filed: March 12, 2021
    Publication date: March 10, 2022
    Inventors: Dongkyun Lim, Youngsin Kim, Kijin Park, Hoju Song, Dongkwan Yang, Sangho Yun, Gyuhyun Lee, Jieun Lee, Seunguk Han, Yoongi Hong
  • Publication number: 20220020758
    Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.
    Type: Application
    Filed: March 4, 2021
    Publication date: January 20, 2022
    Inventors: SEORYONG PARK, SEUNGUK HAN, Jiyoung AHN, Kiseok LEE, YOONYOUNG CHOI, JISEOK HONG
  • Publication number: 20210398569
    Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.
    Type: Application
    Filed: February 5, 2021
    Publication date: December 23, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiseok Hong, Sangho Lee, Seoryong Park, Jiyoung Ahn, Kiseok Lee, Kiseok Lee, Yoonyoung Choi, Seunguk Han
  • Publication number: 20210391259
    Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.
    Type: Application
    Filed: December 21, 2020
    Publication date: December 16, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiyoung Ahn, Seunguk Han, Sunghwan Kim, Seoryong Park, Kiseok Lee, Yoonyoung Choi, Taehee Han, Jiseok Hong
  • Patent number: 8953356
    Abstract: A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunguk Han, Jay-Bok Choi, Dong-Hyun Lee, Namho Jeon
  • Patent number: 8901646
    Abstract: A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namho Jeon, Min-chul Park, Seunguk Han
  • Patent number: 8809930
    Abstract: Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namho Jeon, Jun-Su Kim, Satoru Yamada, Jaehoon Lee, Seunguk Han, Jiyoung Kim, Jin-Seong Lee
  • Publication number: 20130256774
    Abstract: Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.
    Type: Application
    Filed: January 16, 2013
    Publication date: October 3, 2013
    Inventors: Namho JEON, Jun-Su KIM, Satoru YAMADA, Jaehoon LEE, Seunguk HAN, Jiyoung KIM, Jin-Seong LEE
  • Patent number: 8368169
    Abstract: An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: February 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunguk Han, Satoru Yamada, Young Jin Choi
  • Publication number: 20120320655
    Abstract: A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 20, 2012
    Inventors: Seunguk Han, Jay-Bok Choi, Dong-Hyun Lee, Namho Jeon
  • Publication number: 20110108962
    Abstract: An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer.
    Type: Application
    Filed: October 4, 2010
    Publication date: May 12, 2011
    Inventors: Seunguk Han, Satoru Yamada, Young Jin Choi