Abstract: The present invention relates to a compound represented by Formula 1, a pharmaceutically acceptable salt thereof, or an isomer thereof, and a pharmaceutical composition for treating or preventing proteasome-mediated diseases, comprising the same as an active ingredient.

Abstract: A storage device includes a nonvolatile memory; a controller configured to control a write operation of the nonvolatile memory according to a write request received from a host and transmit a response to the write request to the host; and write buffers configured to store write data received with the write request. The controller is further configured to: set a response transmission delay time based on an available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time, transmit the response to the write request to the host after the response transmission delay time passes, and dynamically adjust, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller for controlling a plurality of memory devices in which data is stored may include a host interface configured to receive a request and a logical address corresponding to the request from a host, a processor including multiple cores, each configured to receive the logical address from the host interface and generate mapping information indicating a mapping relationship between the logical address and a physical address and a bitmap storage configured to store a bitmap indicating which core of the multiple cores each of previously-received logical addresses is assigned, wherein the host interface assigns the logical address to one of the multiple cores based on the bitmap.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including buffer blocks and main blocks, and a memory controller configured to control the memory device. The memory controller may include: a buffer block controller configured to control the memory device to store, in at least one of the main blocks, data stored in at least one of the buffer blocks; a mapping table manager configured to generate a P2P mapping table including mapping information between a buffer address that is a physical address of the at least one buffer block and a main address that is a physical address of the at least one main block; and a read operation controller configured to control, when a read request is received, the memory device to read the data based on the main address or the buffer address.

Abstract: A storage device includes a nonvolatile memory; a controller configured to control a write operation of the nonvolatile memory according to a write request received from a host and transmit a response to the write request to the host; and write buffers configured to store write data received with the write request. The controller is further configured to: set a response transmission delay time based on an available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time, transmit the response to the write request to the host after the response transmission delay time passes, and dynamically adjust, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller for controlling a plurality of memory devices in which data is stored may include a host interface configured to receive a request and a logical address corresponding to the request from a host, a processor including multiple cores, each configured to receive the logical address from the host interface and generate mapping information indicating a mapping relationship between the logical address and a physical address and a bitmap storage configured to store a bitmap indicating which core of the multiple cores each of previously-received logical addresses is assigned, wherein the host interface assigns the logical address to one of the multiple cores based on the bitmap.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes: a memory device configured to perform a write operation and a read operation of data; and a controller configured to control the memory device to perform the write operation and the read operation in response to commands received from a host, wherein the controller controls the memory device, in response to a read command corresponding to the read operation among the received commands, to perform the read operation on data at a first address corresponding to the read command and perform a pre-read operation on data at a second address corresponding to a read command not yet received, transmit read data corresponding to the read operation to the host, and store pre-read data corresponding to the pre-read operation.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including buffer blocks and main blocks, and a memory controller configured to control the memory device. The memory controller may include: a buffer block controller configured to control the memory device to store, in at least one of the main blocks, data stored in at least one of the buffer blocks; a mapping table manager configured to generate a P2P mapping table including mapping information between a buffer address that is a physical address of the at least one buffer block and a main address that is a physical address of the at least one main block; and a read operation controller configured to control, when a read request is received, the memory device to read the data based on the main address or the buffer address.

Abstract: In a memory controller for controlling a write operation of a memory device in response to a write request received from a host, the memory controller includes a write buffer and a response message control circuit. The write buffer stores write data received from the host together with the write request. The response message control circuit generates a response message corresponding to the write request and transfers the response message to the host. Also, the response message control circuit determines a response time to transfer the response message, based on a utilization rate of the write buffer.

Abstract: A method for operating a data storage device includes determining a valid page distribution characteristic of used memory blocks; and performing a garbage collection operation based on the valid page distribution characteristic of used memory blocks.

Abstract: A method for operating a data storage device includes determining a valid page distribution characteristic of used memory blocks; and performing a garbage collection operation based on the valid page distribution characteristic of used memory blocks.