Abstract: A memory card includes a first ground terminal arranged in a first row that provides a ground voltage to at least one nonvolatile memory or a memory controller, universal flash storage (UFS) terminals arranged in a second row including a first UFS terminal that provides a second power, a second UFS terminal that provides a reference clock signal, and a third UFS terminal that provides a path for input/output data to the memory controller, and a first power terminal arranged in a third row that provides a first power supply voltage (VCC) to the at least one nonvolatile memory or the memory controller. The memory card has a size defined by a nano subscriber identification module (SIM) card standard, the first ground terminal corresponds to a “C5” terminal of the nano SIM card standard, and the first power terminal corresponds to a “C1” terminal of the nano SIM card standard.

Abstract: A memory card includes a first ground terminal arranged in a first row that provides a ground voltage to at least one nonvolatile memory or a memory controller, universal flash storage (UFS) terminals arranged in a second row including a first UFS terminal that provides a second power, a second UFS terminal that provides a reference clock signal, and a third UFS terminal that provides a path for input/output data to the memory controller, and a first power terminal arranged in a third row that provides a first power supply voltage (VCC) to the at least one nonvolatile memory or the memory controller. The memory card has a size defined by a nano subscriber identification module (SIM) card standard, the first ground terminal corresponds to a “C5” terminal of the nano SIM card standard, and the first power terminal corresponds to a “C1” terminal of the nano SIM card standard.

Abstract: A memory card includes a substrate, first row terminals and second row terminals. The substrate has a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction. The first row terminals are arranged adjacent to an insertion side edge of the substrate, the first row terminals including a first power terminal, the insertion side edge being one of the first pair of side edges. The second row terminals are arranged further from the insertion side edge than the first row terminals, the second row terminals including a second power terminal. At least one recessed terminal among the first and second row terminals includes a recess area in an exposed surface of the at least one terminal.

Abstract: A memory card includes a substrate, first row terminals and second row terminals. The substrate has a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction. The first row terminals are arranged adjacent to an insertion side edge of the substrate, the first row terminals including a first power terminal, the insertion side edge being one of the first pair of side edges. The second row terminals are arranged further from the insertion side edge than the first row terminals, the second row terminals including a second power terminal. At least one recessed terminal among the first and second row terminals includes a recess area in an exposed surface of the at least one terminal.

Abstract: A memory card includes a substrate, first row terminals and second row terminals. The substrate has a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction. The first row terminals are arranged adjacent to an insertion side edge of the substrate, the first row terminals including a first power terminal, the insertion side edge being one of the first pair of side edges. The second row terminals are arranged further from the insertion side edge than the first row terminals, the second row terminals including a second power terminal. At least one terminal among the first and second row terminals includes a recess area in an exposed surface of the at least one terminal.

Abstract: A memory card includes a substrate, first row terminals and second row terminals. The substrate has a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction. The first row terminals are arranged adjacent to an insertion side edge of the substrate, the first row terminals including a first power terminal, the insertion side edge being one of the first pair of side edges. The second row terminals are arranged further from the insertion side edge than the first row terminals, the second row terminals including a second power terminal. At least one terminal among the first and second row terminals includes a recess area in an exposed surface of the at least one terminal.

Abstract: A non-volatile memory device having respective parallel queues is disclosed. The non-volatile memory device includes a plurality of concurrently addressable units. The non-volatile memory device has respective queues for the concurrently addressable units, and transfers a second command to respective queues for the remaining concurrently addressable units while a first command is executed in a part of the concurrently addressable units, and executes a second command in the remaining concurrently addressable units. Accordingly, non-volatile memory device may concurrently access the concurrently addressable units in parallel, and may have high speed.

Abstract: A non-volatile memory device having respective parallel queues is disclosed. The non-volatile memory device includes a plurality of concurrently addressable units. The non-volatile memory device has respective queues for the concurrently addressable units, and transfers a second command to respective queues for the remaining concurrently addressable units while a first command is executed in a part of the concurrently addressable units, and executes a second command in the remaining concurrently addressable units. Accordingly, non-volatile memory device may concurrently access the concurrently addressable units in parallel, and may have high speed.