Patents by Inventor Seung Wan Shin
Seung Wan Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10685916Abstract: A fan-out semiconductor package includes a frame comprising wiring layers, and a dummy layer, and having a recessed portion on a bottom surface on which a stopper layer is disposed; a semiconductor chip disposed in the recessed portion such that an inactive surface opposes the stopper layer; a first interconnect structure disposed on the connection pad; a second interconnect structure disposed on the outermost wiring layer; a dummy structure disposed on the dummy layer; an encapsulant encapsulating at least portions of the frame, the semiconductor chip, the first interconnect structure, the second interconnect structure, and the dummy structure, and filling at least a portion of the recessed portion; and a connection member disposed on the frame and an active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to first and second metal bumps. The dummy structure has sloped side surfaces.Type: GrantFiled: February 26, 2019Date of Patent: June 16, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Wan Shin, Ho Jun Jung, Seung Chul Oh
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Publication number: 20200075487Abstract: A fan-out semiconductor package includes a frame comprising wiring layers, and a dummy layer, and having a recessed portion on a bottom surface on which a stopper layer is disposed; a semiconductor chip disposed in the recessed portion such that an inactive surface opposes the stopper layer; a first interconnect structure disposed on the connection pad; a second interconnect structure disposed on the outermost wiring layer; a dummy structure disposed on the dummy layer; an encapsulant encapsulating at least portions of the frame, the semiconductor chip, the first interconnect structure, the second interconnect structure, and the dummy structure, and filling at least a portion of the recessed portion; and a connection member disposed on the frame and an active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to first and second metal bumps. The dummy structure has sloped side surfaces.Type: ApplicationFiled: February 26, 2019Publication date: March 5, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Wan SHIN, Ho Jun JUNG, Seung Chul OH
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Patent number: 10347585Abstract: A fan-out semiconductor package includes: a first semiconductor chip having a first active surface having first connection pads; a first encapsulant encapsulating the first semiconductor chip; a first connection member disposed on the first active surface and including a first redistribution layer electrically connected to the first connection pads; a second semiconductor chip having a second active surface having second connection pads; a second encapsulant covering the first connection member and encapsulating the second semiconductor chip; a second connection member disposed on the second active surface and including a second redistribution layer electrically connected to the second connection pads; and a third via penetrating through the second encapsulant, connecting the first redistribution layer and the second redistribution layer to each other, and including a metal post connected to the first redistribution layer and a via conductor disposed on the metal post and connected to the second redistributioType: GrantFiled: April 5, 2018Date of Patent: July 9, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wan Shin, Seung Chul Oh
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Publication number: 20190122990Abstract: A fan-out semiconductor package includes: a first semiconductor chip having a first active surface having first connection pads; a first encapsulant encapsulating the first semiconductor chip; a first connection member disposed on the first active surface and including a first redistribution layer electrically connected to the first connection pads; a second semiconductor chip having a second active surface having second connection pads; a second encapsulant covering the first connection member and encapsulating the second semiconductor chip; a second connection member disposed on the second active surface and including a second redistribution layer electrically connected to the second connection pads; and a third via penetrating through the second encapsulant, connecting the first redistribution layer and the second redistribution layer to each other, and including a metal post connected to the first redistribution layer and a via conductor disposed on the metal post and connected to the second redistributioType: ApplicationFiled: April 5, 2018Publication date: April 25, 2019Inventors: Seung Wan SHIN, Seung Chul OH
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Publication number: 20160198568Abstract: A printed circuit board includes a first insulating layer including a first circuit pattern, a second insulating layer including a second circuit pattern, and a dummy pattern disposed in the first insulating layer and the second insulating layer, in which the first and second insulating layers are made of different materials. An electronic component module includes a printed circuit board and an electronic component mounted on the printed circuit board.Type: ApplicationFiled: January 4, 2016Publication date: July 7, 2016Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Mi Jin PARK, Kyoung Moo HARR, Seung Wan SHIN
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Patent number: 9196506Abstract: A method for manufacturing an interposer includes forming a via hole in an insulation plate including a resin or a ceramic; simultaneously forming resists for a first upper redistribution layer on the top surface of the insulation plate, and a resistor for a lower redistribution layer on the bottom surface of the insulation plate; plating copper to fill the via hole and simultaneously forming the first upper redistribution layer and the lower redistribution layer along a designed circuit pattern; and forming a first upper protection layer and a lower protection layer to expose a portion of the first upper redistribution layer and a portion of the lower redistribution layer.Type: GrantFiled: October 1, 2012Date of Patent: November 24, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hyung Jin Jeon, Jong In Ryu, Seung Wan Shin, Seon Hee Moon, Young Do Kweon, Seung Wook Park
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Patent number: 8582314Abstract: There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.Type: GrantFiled: August 10, 2010Date of Patent: November 12, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Young Do Kweon, Seung Wan Shin, Mi Jin Park, Kyung Seob Oh
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Publication number: 20130139753Abstract: Disclosed herein is an apparatus for manufacturing a substrate. The apparatus for manufacturing a substrate includes: a reaction gas ejector ejecting reaction gas; a lift pin supporting the substrate and having a header contacting a rear surface of the substrate; and a support chuck having a lift pin insertion unit inserted with the lift pin and moving vertically and including a ring in a header insertion portion into which the header is inserted in the lift pin insertion unit.Type: ApplicationFiled: March 1, 2012Publication date: June 6, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Joon Seok Kang, Seung Wan Shin
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Publication number: 20120161323Abstract: Disclosed herein are a substrate for a package and a method for manufacturing the same. The substrate for the package according to the present invention includes: a base substrate; a photosensitive insulating layer formed on one surface of the base substrate and having a roughness formed on a surface thereof; and a seed layer formed on one surface of the photosensitive insulating layer.Type: ApplicationFiled: March 4, 2011Publication date: June 28, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yoon Su KIM, Seon Hee MOON, Seung Wan SHIN, Young Do KWEON
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Publication number: 20120084977Abstract: Disclosed herein is a method of manufacturing a block module including: mounting an electronic part on a base substrate on which a ground terminal is formed; forming a lead frame to extend to the outside of the base substrate from the ground terminal; connecting a flexible printed circuit to a circuit layer on the base substrate; forming a mold to surround the base substrate; cutting the lead frame and exposing the cut surface of the lead frame to the outside of the mold; and forming a metal coating layer connected to the lead frame on the mold, whereby the metal coating layer is formed to surround the mold to interrupt the electromagnetic waves and the metal coating layer is connected to the ground terminal by the lead frame to make the process simple.Type: ApplicationFiled: October 7, 2011Publication date: April 12, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook PARK, Young Do KWEON, Ju Pyo HONG, Seung Wan SHIN, Kyung Seob OH
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Publication number: 20110176285Abstract: There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.Type: ApplicationFiled: August 10, 2010Publication date: July 21, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Young Do Kweon, Seung Wan Shin, Mi Jin Park, Kyung Seob Oh
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Publication number: 20110061911Abstract: An interposer includes: an insulation plate where a via is formed, the insulation plate including a resin or a ceramic; a first upper redistribution layer electrically connected to the via along a circuit pattern designed on the top surface of the insulation plate; a first upper protection layer laminated to expose a portion of the first upper redistribution layer and protecting the first upper redistribution layer; a second upper redistribution layer electrically connected to the first upper redistribution layer and laminated along a designed circuit pattern designed; a second upper protection layer laminated to expose a portion of the second upper redistribution layer and protecting the second upper redistribution layer; and an under bump metallization (UBM) formed at the exposed portion of the second upper redistribution layer.Type: ApplicationFiled: December 17, 2009Publication date: March 17, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO. LTD.Inventors: Hyung Jin Jeon, Jong In Ryu, Seung Wan Shin, Seon Hee Moon, Young Do Kweon, Seung Wook Park