Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Abstract: A surface inspection apparatus and method of inspecting chip surfaces includes a laser generator that generates a periodic CW laser and is transformed into an inspection laser beam having a beam size smaller than a surface size of the chip. Thus, the inspection laser beam is irradiated onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously heated. Thermal waves are detected in response to the inspection laser beam and thermal images are generated corresponding to the thermal waves. A surface image is generated by a lock-in thermography technique and hold exponent analysis of the thermal image, thereby generating surface image in which a surface defect is included. Time and accuracy of the surface inspection process is improved.

Abstract: A surface inspection apparatus and method of inspecting chip surfaces includes a laser generator that generates a periodic CW laser and is transformed into an inspection laser beam having a beam size smaller than a surface size of the chip. Thus, the inspection laser beam is irradiated onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously heated. Thermal waves are detected in response to the inspection laser beam and thermal images are generated corresponding to the thermal waves. A surface image is generated by a lock-in thermography technique and hold exponent analysis of the thermal image, thereby generating surface image in which a surface defect is included. Time and accuracy of the surface inspection process is improved.

Abstract: Provided are a wire bonding apparatus and a method wire bonding and manufacturing a semiconductor device using the same. The wire bonding apparatus includes a heater block configured to support a stack including a chip mounting frame and a plurality of chips stacked on the chip mounting frame. The heater block is configured to supply heat to a first portion of the stack. The apparatus further includes a chip heating unit disposed at a different height from the heater block. The chip heating unit is configured to supply heat to a second portion of the stack at a different height from the first portion.

Abstract: Provided are a wire bonding apparatus and a method wire bonding and manufacturing a semiconductor device using the same. The wire bonding apparatus includes a heater block configured to support a stack including a chip mounting frame and a plurality of chips stacked on the chip mounting frame. The heater block is configured to supply heat to a first portion of the stack. The apparatus further includes a chip heating unit disposed at a different height from the heater block. The chip heating unit is configured to supply heat to a second portion of the stack at a different height from the first portion.

Abstract: A multi-chip package may include a package substrate, a plurality of semiconductor chips and conductive connecting members. The semiconductor chips may be sequentially stacked on the package substrate. Each of the semiconductor chips may include a signal pad and a test pad. The conductive wires may be electrically connected between the signal pad of an upper semiconductor chip among the semiconductor chips and the package substrate via the test pad of a lower semiconductor chip under the upper semiconductor chip. The test pad may be converted into the dummy pad by cutting a fuse.

Abstract: Provided are a semiconductor package in which wiring layers connected to a semiconductor chip electrically contact circuit patterns of a substrate and a method of manufacturing the same. The semiconductor package includes the substrate and the semiconductor chip. The substrate includes a first concave portion disposed on the upper surface thereof and a plurality of the circuit patterns disposed adjacent to the first concave portion. The semiconductor chip is mounted in the substrate to correspond to the concave portion. The semiconductor chip comprises a wafer, pads disposed on the wafer, and wiring layers disposed on the upper surface and on one side surface of the wafer, wherein first portions disposed on the upper surface of the wafer are connected to the pads and second portions disposed on the one side surface of the wafer contact the circuit patterns of the substrate.