Patents by Inventor Seung-won Lim
Seung-won Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7986531Abstract: Provided are a power system module allowing a user's requirements to be easily met, and having economic practicality and high integration, and a manufacturing method thereof. The power system module includes a plastic case, a molding type power module package, a control circuit board, and at least one external terminal. The plastic case defines a bottom and a side wall. The molding type power module package is fixed to the bottom of the plastic case and includes at least a power device therein. The control circuit board is fixed to the side wall of the plastic case, includes at least a control device mounted thereon which is electrically connected to the power module package. The external terminal protrudes to outside the plastic case and is electrically connected to the control circuit board.Type: GrantFiled: March 11, 2010Date of Patent: July 26, 2011Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim, Seung-han Paek, Sung-min Park
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Patent number: 7951645Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.Type: GrantFiled: February 9, 2010Date of Patent: May 31, 2011Assignee: Fairchild Korea Semiconductor, LtdInventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
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Publication number: 20110076804Abstract: Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.Type: ApplicationFiled: December 8, 2010Publication date: March 31, 2011Inventors: Man-kyo Jong, Joon-seo Son, Seung-won Lim, O-soeb Jeon
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Patent number: 7863725Abstract: Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.Type: GrantFiled: November 18, 2008Date of Patent: January 4, 2011Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Man-kyo Jong, Joon-seo Son, Seung-won Lim, O-soeb Jeon
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Patent number: 7847395Abstract: A package and a package assembly for a power device having a high operation voltage and impulse voltage are provided. The package assembly for a power device comprises an assembly wherein the power device is encapsulated and electrically connected to a lead protruding outside the package, and an isolation spacer filling a clearance distance between the package and a heat sink attached to the package.Type: GrantFiled: February 28, 2007Date of Patent: December 7, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Seung-han Baek, Seung-won Lim
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Publication number: 20100289137Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.Type: ApplicationFiled: July 28, 2010Publication date: November 18, 2010Applicant: Fairchild Korea Semiconductor, Ltd.Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
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Patent number: 7808103Abstract: Provided is a semiconductor package, and in particular a semiconductor package which is capable of electrically connecting to the outside without a lead.Type: GrantFiled: January 7, 2009Date of Patent: October 5, 2010Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Sung-min Park, Keun-hyuk Lee, Seung-Won Lim
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Patent number: 7786570Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.Type: GrantFiled: January 23, 2009Date of Patent: August 31, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Joo-Yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
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Publication number: 20100165576Abstract: Provided are a power system module allowing a user's requirements to be easily met, and having economic practicality and high integration, and a manufacturing method thereof. The power system module includes a plastic case, a molding type power module package, a control circuit board, and at least one external terminal. The plastic case defines a bottom and a side wall. The molding type power module package is fixed to the bottom of the plastic case and includes at least a power device therein. The control circuit board is fixed to the side wall of the plastic case, includes at least a control device mounted thereon which is electrically connected to the power module package. The external terminal protrudes to outside the plastic case and is electrically connected to the control circuit board.Type: ApplicationFiled: March 11, 2010Publication date: July 1, 2010Applicant: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim, Seung-han Paek, Sung-min Park
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Publication number: 20100167470Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.Type: ApplicationFiled: February 9, 2010Publication date: July 1, 2010Applicant: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
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Publication number: 20100155914Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.Type: ApplicationFiled: December 21, 2009Publication date: June 24, 2010Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-kyuk Lee, Yun-hwa Choi
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Publication number: 20100140786Abstract: Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more semiconductor chips and exposed from the sealing member; and an external bonding member electrically connected to the one or more semiconductor chips and electrically connecting an external circuit board exposed from the sealing member.Type: ApplicationFiled: December 7, 2009Publication date: June 10, 2010Applicant: FAIRCHILD KOREA SEMICONDUCTOR LTD.Inventors: Keun-hyuk LEE, Young-sun KO, Seung-won LIM, Man-kyo JUNG, Seung-yong CHOI
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Patent number: 7714428Abstract: A high power semiconductor package includes a substrate including a base metal layer, a base insulation layer formed on the base metal layer, and a plurality of conductive patterns formed on the base insulation layer. In one embodiment one or more high power semiconductor chips are mounted on the substrate, each including a plurality of bonding pads, one or more first package leads having end portions that are electrically connected to the corresponding conductive patterns, and a second lead having an end portion electrically which may be connected to either the base insulation layer or the base metal layer.Type: GrantFiled: December 6, 2007Date of Patent: May 11, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim
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Patent number: 7706146Abstract: Provided are a power system module allowing a user's requirements to be easily met, and having economic practicality and high integration, and a manufacturing method thereof. The power system module includes a plastic case, a molding type power module package, a control circuit board, and at least one external terminal. The plastic case defines a bottom and a side wall. The molding type power module package is fixed to the bottom of the plastic case and includes at least a power device therein. The control circuit board is fixed to the side wall of the plastic case, includes at least a control device mounted thereon which is electrically connected to the power module package. The external terminal protrudes to outside the plastic case and is electrically connected to the control circuit board.Type: GrantFiled: April 5, 2007Date of Patent: April 27, 2010Assignee: Fairchild Korea Semiconductor LtdInventors: Keun-hyuk Lee, Seung-won Lim, Seung-han Paek, Sung-min Park
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Patent number: 7701048Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.Type: GrantFiled: May 3, 2007Date of Patent: April 20, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
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Patent number: 7687903Abstract: Provided are a power module including a power package and a control package that are provided separately and can be highly integrated, and method of fabricating the power module. The power module includes: a molded power package including at least one power device on a first lead frame; and a molded control package vertically stacked on the power package, and including at least one control device on a second lead frame. A first part of the first lead frame and a first part of the second lead frame are coupled to each other so that the power package and the control package can be electrically coupled to each other.Type: GrantFiled: July 24, 2008Date of Patent: March 30, 2010Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Joon-seo Son, Seung-won Lim, O-seob Jeon
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Patent number: 7675148Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.Type: GrantFiled: February 28, 2008Date of Patent: March 9, 2010Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi
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Publication number: 20090243061Abstract: Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips.Type: ApplicationFiled: March 27, 2009Publication date: October 1, 2009Inventors: Gwi-gyeon Yang, Seung-won Lim
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Publication number: 20090243079Abstract: Provided is a semiconductor device package including a substrate formed of a silicon (Si)-based material. The semiconductor device package includes a first substrate which comprises first and second principal planes which are opposite each other, and a substrate body layer disposed between the first and second principal planes, the substrate body layer being formed of a silicon (Si)-based material; and at least one first semiconductor device which is mounted on the first principal plane.Type: ApplicationFiled: March 17, 2009Publication date: October 1, 2009Inventors: Seung-won Lim, O-seob Jeon, Seung-yong Choi, Joon-seo Son, Man-kyo Jong
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Publication number: 20090243078Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.Type: ApplicationFiled: March 18, 2009Publication date: October 1, 2009Inventors: Seung-won Lim, O-soeb Jeon, Joon-seo Son, Byoung-ok Lee, Man-kyo Jong