Patents by Inventor Seung Wook Yoon
Seung Wook Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11957180Abstract: An aerosol generating device includes: a holder configured to generate aerosols; and a cradle which displays, on the display, data obtained from the sensor and an indicator for activating a user interface, outputs through the user interface a plurality of pre-stored temperature profiles in response to a first user input of selecting the indicator, and in response to a second user input of selecting any one of the plurality of the pre-stored temperature profiles, transmits the selected temperature profile to the holder such that the holder controls a temperature profile used to heat an aerosol generating material based on the selected temperature profile.Type: GrantFiled: October 21, 2020Date of Patent: April 16, 2024Assignee: KT&G CORPORATIONInventors: Sung Wook Yoon, Seung Won Lee, Dae Nam Han
-
Patent number: 11961764Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: GrantFiled: April 15, 2021Date of Patent: April 16, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
-
Publication number: 20240108052Abstract: An embodiment of the present disclosure discloses tobacco material including: a center portion including a flavor material; and an outer portion including a tobacco mixture, wherein the outer portion surrounds the center portion.Type: ApplicationFiled: April 12, 2022Publication date: April 4, 2024Applicant: KT&G CORPORATIONInventors: Seok Su JANG, Sun Hwan JUNG, Hyeon Tae KIM, Jun Won SHIN, Dae Nam HAN, Yong Hwan KIM, Sung Wook YOON, Seung Won LEE
-
Publication number: 20240097088Abstract: A backplane substrate, a display device, and a tiled display device are provided. The backplane substrate of a display device includes subpixels. The backplane substrate includes a support substrate, a circuit layer on a first surface of the support substrate and including pixel drivers corresponding to the subpixels, respectively, an electrode layer on the circuit layer and including an anode and a cathode corresponding to an emission area of each of the subpixels, a bank layer on the circuit layer and corresponding to an area around the emission area of each of the subpixels, and a valley spaced from edges of the support substrate and penetrating at least the bank layer.Type: ApplicationFiled: August 30, 2023Publication date: March 21, 2024Inventors: Jin Ho HYUN, Seung Wook KWON, Hee Chang YOON, Hye Min LEE
-
Patent number: 11930850Abstract: An aerosol generating device includes an accommodation portion configured to accommodate an aerosol generating article through an opening, a heater configured to heat the accommodation portion and move along a longitudinal direction of the accommodation portion; and a heater support that supports the heater and move the heater along the longitudinal direction of the accommodation portion, wherein the heater moves between a first position corresponding to a first point of the aerosol generating article and a second position corresponding to a second point of the aerosol generating article, and wherein the first position and the second position differ according to specifications of the aerosol generating article.Type: GrantFiled: July 29, 2020Date of Patent: March 19, 2024Assignee: KT&G CORPORATIONInventors: Sung Wook Yoon, Seung Won Lee, Dae Nam Han
-
Patent number: 11930840Abstract: An aerosol generating article includes an aerosol generator including a first aerosol generating material which does not include nicotine; a tobacco filler arranged adjacent to an end of the aerosol generator and including a second aerosol generating material including nicotine; a cooler arranged adjacent to an end of the tobacco filler and configured to cool aerosol; and a mouth piece arranged adjacent to an end of the cooler.Type: GrantFiled: June 11, 2020Date of Patent: March 19, 2024Assignee: KT&G CORPORATIONInventors: Seung Won Lee, Sung Wook Yoon, Dae Nam Han, Yong Hwan Kim
-
Patent number: 11937502Abstract: A condensed cyclic compound and an organic light-emitting device including the condensed cyclic compound are provided. The condensed cyclic compound is represented by Formula 1. The A3 ring of Formula 1 is a group represented by Formula 2A or a group represented by Formula 2B. The organic light-emitting device includes: a first electrode; a second electrode; and an organic layer between the first electrode and the second electrode and including an emission layer, the organic layer including at least one of the condensed cyclic compound represented by Formula 1.Type: GrantFiled: April 13, 2016Date of Patent: March 19, 2024Assignees: Samsung Display Co., Ltd., Research & Business Foundation Sungkyunkwan UniversityInventors: Sung-Wook Kim, Myeong-Suk Kim, Hwan-Hee Cho, Sam-Il Kho, Seung-Soo Yoon, Changwoong Chu
-
Publication number: 20230180002Abstract: The present invention relates to a PUF-based IoT device authentication technique, and more specifically, to a PUF-based IoT device using channel state information, and an authentication method thereof. According to an embodiment of the present invention, security of an authentication key may be strengthened by simultaneously utilizing a PUF-based authentication method and an RF characteristic-based authentication method.Type: ApplicationFiled: June 15, 2022Publication date: June 8, 2023Applicant: Gwangju Institute of Science and TechnologyInventors: Eui Seok HWANG, Seung Wook YOON, Seung Nam HAN
-
Publication number: 20220093417Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Applicant: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
-
Patent number: 11257729Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.Type: GrantFiled: September 1, 2019Date of Patent: February 22, 2022Inventors: Thomas J. Strothmann, Seung Wook Yoon, Yaojian Lin
-
Patent number: 11222793Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: GrantFiled: November 19, 2019Date of Patent: January 11, 2022Assignee: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
-
Publication number: 20210233815Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Applicant: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
-
Patent number: 11011423Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: GrantFiled: November 29, 2018Date of Patent: May 18, 2021Assignee: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
-
Patent number: 10903304Abstract: A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties.Type: GrantFiled: March 16, 2017Date of Patent: January 26, 2021Assignee: STATS ChipPAC Pte. Ltd.Inventors: Meenakshi Padmanathan, Seung Wook Yoon, YongTaek Lee
-
Patent number: 10622293Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.Type: GrantFiled: January 27, 2016Date of Patent: April 14, 2020Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.Inventors: Seung Wook Yoon, Jose A. Caparas, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao, Jianmin Fang
-
Publication number: 20200090954Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: ApplicationFiled: November 19, 2019Publication date: March 19, 2020Applicant: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
-
Publication number: 20200006177Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.Type: ApplicationFiled: September 1, 2019Publication date: January 2, 2020Applicant: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Seung Wook Yoon, Yaojian Lin
-
Method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
Patent number: 10515828Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: GrantFiled: September 23, 2016Date of Patent: December 24, 2019Assignee: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu -
Patent number: 10475779Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.Type: GrantFiled: August 14, 2017Date of Patent: November 12, 2019Assignee: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Kang Chen, Seung Wook Yoon
-
Patent number: 10446459Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.Type: GrantFiled: June 9, 2017Date of Patent: October 15, 2019Assignee: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Seung Wook Yoon, Yaojian Lin