Abstract: A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

Abstract: A driving voltage provider includes: a PLL circuit for generating clock signals with different phases according to a divider value; a DC-DC converter for generating a PWM signal according to the frequency of a first clock signal, and providing a driving voltage based on the duty ratio of the PWM signal; a first tuning circuit for outputting a first tuning signal having a first logic level when the logic levels of first and second sampling signals obtained by sampling the PWM signal at transition times of different clock signals are different, and outputting the first tuning signal having a second logic level when the first and second sampling signals have the same logic level; and a divider value determiner for decreasing the divider value when the logic level of the first tuning signal is the first logic level.

Abstract: A display device includes a display panel including gate lines, data lines, and pixels individually connected to a corresponding gate line and data line, a gate driver driving the gate lines, a data driver driving the data lines, and a driving controller. The driving controller receives, from an external source, first image signals and a variable frequency signal indicating an operation frequency (frame rate) for the display device. The driving controller converts the first image signals to second image signals by adding a compensation value corresponding to the operation frequency to the first image signals, and outputs the second image signals to the data driver. Embodiments may compensate for luminance reduction/variation and reduce image artifacts that otherwise occur due to variable frequency operation. An alternative embodiment dynamically controls an amount of light output from a backlight according to the variable frequency signal.

Abstract: A display device includes a display panel which includes gate lines and data lines, a gate driver electrically connected to the gate lines, a temperature sensor which includes at least three temperature sensing circuits which are disposed adjacent to the gate driver, and a voltage generating circuit which outputs a test voltage to each of the temperature sensing circuits and outputs a clock signal, which is compensated based on a result voltage having a lowest voltage level among result voltages provided from the temperature sensing circuits, to the gate driver.

Abstract: A display apparatus includes a display panel, a data driving circuit, and a gate driving circuit. The display panel is configured to display an image and includes a gate line and a data line. The data driving circuit is configured to output a data signal to the data line. The gate driving circuit is configured to output a gate signal to the gate line and to control a kick-back time of the gate signal according to a temperature of the display panel. The kick-back time is a time when the gate signal is decreased from a gate on voltage to a kick-back voltage that is between the gate on voltage and a gate off voltage.

Abstract: A driving voltage provider includes: a PLL circuit for generating clock signals with different phases according to a divider value; a DC-DC converter for generating a PWM signal according to the frequency of a first clock signal, and providing a driving voltage based on the duty ratio of the PWM signal; a first tuning circuit for outputting a first tuning signal having a first logic level when the logic levels of first and second sampling signals obtained by sampling the PWM signal at transition times of different clock signals are different, and outputting the first tuning signal having a second logic level when the first and second sampling signals have the same logic level; and a divider value determiner for decreasing the divider value when the logic level of the first tuning signal is the first logic level.

Abstract: A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

Abstract: A display device includes a display panel including gate lines, data lines, and pixels individually connected to a corresponding gate line and data line, a gate driver driving the gate lines, a data driver driving the data lines, and a driving controller. The driving controller receives, from an external source, first image signals and a variable frequency signal indicating an operation frequency (frame rate) for the display device. The driving controller converts the first image signals to second image signals by adding a compensation value corresponding to the operation frequency to the first image signals, and outputs the second image signals to the data driver. Embodiments may compensate for luminance reduction/variation and reduce image artifacts that otherwise occur due to variable frequency operation. An alternative embodiment dynamically controls an amount of light output from a backlight according to the variable frequency signal.

Abstract: A display device includes a display panel which includes gate lines and data lines, a gate driver electrically connected to the gate lines, a temperature sensor which includes at least three temperature sensing circuits which are disposed adjacent to the gate driver, and a voltage generating circuit which outputs a test voltage to each of the temperature sensing circuits and outputs a clock signal, which is compensated based on a result voltage having a lowest voltage level among result voltages provided from the temperature sensing circuits, to the gate driver.

Abstract: There is provided a display apparatus comprising: a backlight configured to output a first and a second light having a first and second color during a first and second field of a frame; a mapper configured to map an input image signal into a first and a second mapping data corresponding to the first and second light; a compensator configured to compensate a first and a second color mapping data on a basis of a first and a second DCC compensation data so as to generate a first and second color output image data; and a liquid crystal panel comprising a transmissive sub pixel configured to modulate the first and second light on a basis of the first and second color output data to display a first image having the first color and a second image having the second color.

Abstract: A display device includes a display unit that includes a plurality of unit areas, wherein each of the plurality of unit areas includes a plurality of pixels arranged in a matrix format, the plurality of pixels include a plurality of high-level pixels receiving a data voltage of relatively high luminance and a plurality of low-level pixels receiving a data voltage of relatively low luminance with respect to the same image data, and in the unit areas, high-level pixel pairs and low-level pixel pairs are alternately arranged in a row direction, and one high-level pixel and one low-level pixel are alternately arranged in a column direction.

Abstract: A display apparatus includes a display panel, a data driving part and a gate driving part. The gate driving part outputs gate signals to gate lines, respectively, increases the gate signal from a first gate off voltage to a gate on voltage, decreases the gate signal from the gate on voltage to the first gate off voltage, decreases the gate signal from the first gate off voltage to a second gate off voltage in a slope less than a slope in which the gate signal decreases from the gate on voltage to the first gate off voltage, during P (P is a natural number) horizontal time in which P gate line of the gate lines is driven, and increases the gate signal from the second gate off voltage to the first gate off voltage.

Abstract: A display apparatus includes a display panel, a data driving part and a gate driving part. The gate driving part outputs gate signals to gate lines, respectively, increases the gate signal from a first gate off voltage to a gate on voltage, decreases the gate signal from the gate on voltage to the first gate off voltage, decreases the gate signal from the first gate off voltage to a second gate off voltage in a slope less than a slope in which the gate signal decreases from the gate on voltage to the first gate off voltage, during P (P is a natural number) horizontal time in which P gate line of the gate lines is driven, and increases the gate signal from the second gate off voltage to the first gate off voltage.

Abstract: A display apparatus including: gate lines extending in a first direction; data lines extending in a second direction intersecting the first direction; pixels connected to corresponding ones of the gate lines and data lines; a gate driver to drive the gate lines in response to a gate clock signal; a data driver to drive the data lines; a memory to store charge share signals corresponding to the gate lines; a timing controller controlling the data driver and the gate driver, in response to an externally input control signal and an image signal, and to output a gate pulse signal to the gate lines; and a clock generator configured to generate the gate clock signal in response to the gate pulse signal. The timing controller is configured to output the gate pulse signals according to the charge share signals.

Abstract: A display apparatus includes a display panel, a data driving circuit, and a gate driving circuit. The display panel is configured to display an image and includes a gate line and a data line. The data driving circuit is configured to output a data signal to the data line. The gate driving circuit is configured to output a gate signal to the gate line and to control a kick-back time of the gate signal according to a temperature of the display panel. The kick-back time is a time when the gate signal is decreased from a gate on voltage to a kick-back voltage that is between the gate on voltage and a gate off voltage.

Abstract: A method of driving a display panel, the method including outputting video data to a display panel during an N-th (N is a natural number) frame, outputting video data to the display panel during an (N+1)-th frame, comparing polarities of video data of the N-th frame and corresponding polarities of video data of the (N+1)-th frame, and controlling polarities of video data of an (N+2)-th frame, according to the result of the comparison.

Abstract: There is provided a display apparatus comprising: a backlight configured to output a first and a second light having a first and second color during a first and second field of a frame; a mapper configured to map an input image signal into a first and a second mapping data corresponding to the first and second light; a compensator configured to compensate a first and a second color mapping data on a basis of a first and a second DCC compensation data so as to generate a first and second color output image data; and a liquid crystal panel comprising a transmissive sub pixel configured to modulate the first and second light on a basis of the first and second color output data to display a first image having the first color and a second image having the second color.

Abstract: A display apparatus including a plurality of pixels arranged in association with a plurality of gate lines and a plurality of data lines crossing the gate lines, a data driver configured to drive the data lines, a gate driving unit configured to drive the gate lines in synchronization with a gate control signal, and a timing controller configured to control the data driver and the gate driving unit in response to an image signal and a control signal from an exterior. The timing controller outputs the gate control signal including a plurality of pulses respectively corresponding to the gate lines and an enable time of each pulse of the gate control signal is set according to a position of a corresponding gate line of the gate lines.

Abstract: A display apparatus includes a display panel, a panel driver, a light source part, and a light source driver. The display panel includes a first sub-pixel having a first primary color, a second sub-pixel having a second primary color, and a third sub-pixel having a white color. The panel driver drives the first, second, and third sub-pixels. The light source part provides the display panel with light. The light source part includes a first light source and a second light source. The first light source emits the light having a mixed color of the first primary color and the second primary color. The second light source emits the light having a third primary color. The first and second light sources are alternately turn on in one frame period. A turn-on order of the first and second light sources is changed by a unit of at least one frame period.

Abstract: A display apparatus includes pixels connected to gate lines and data lines crossing the gate lines, a data driver which drives the data lines, a gate driver which drives the gate lines, a timing controller which controls the data driver and the gate driver in response to an image signal and a control signal and outputs a first kickback signal and a second kickback signal, and a voltage generator which outputs a first gate-on voltage and a second gate-on voltage in response to the first and second kickback signals to drive the gate lines. The gate driver drives a first group of gate lines in response to the first gate-on voltage and drives a second group of the gate lines in response to the second gate-on voltage.