Abstract: A memory device includes a memory cell array, an information register and a prefetch circuit. The memory cell array stores a valid data array, a base array and a target data array, where the valid data array includes valid elements among elements of first data, the base array includes position elements indicating position values corresponding to the valid elements and the target data array includes target elements of second data corresponding to the position values. The information register stores indirect memory access information including a start address of the target data array and a unit size of the target elements. The prefetch circuit prefetches, based on the indirect memory access information, the target elements corresponding to the position elements that are read from the memory cell array.

Abstract: A storage device includes a non-volatile memory including a first block, a second block and a block management area that stores an initial data write time and a final data write time for each of the first block and the second block. The storage device also includes a memory controller that determines a creation time and a modification time for first data in response to a permanently delete command identifying the first data, selects at least one of the first block and the second block to be permanently deleted by comparing the initial data write time and the final data write time for each of the first block and the second block with the creation time and the modification time, and permanently deletes the selected at least one of the first block and the second block.

Abstract: A memory device includes a memory cell array, an information register and a prefetch circuit. The memory cell array stores a valid data array, a base array and a target data array, where the valid data array includes valid elements among elements of first data, the base array includes position elements indicating position values corresponding to the valid elements and the target data array includes target elements of second data corresponding to the position values. The information register stores indirect memory access information including a start address of the target data array and a unit size of the target elements. The prefetch circuit prefetches, based on the indirect memory access information, the target elements corresponding to the position elements that are read from the memory cell array.

Abstract: A storage device includes a non-volatile memory including a first block, a second block and a block management area that stores an initial data write time and a final data write time for each of the first block and the second block. The storage device also includes a memory controller that determines a creation time and a modification time for first data in response to a permanently delete command identifying the first data, selects at least one of the first block and the second block to be permanently deleted by comparing the initial data write time and the final data write time for each of the first block and the second block with the creation time and the modification time, and permanently deletes the selected at least one of the first block and the second block.

Abstract: Provided is a method of writing data of a storage system. The method includes causing a host to issue a first writing command; causing the host, when a queue depth of the first writing command is a first value, to store the first writing command in an entry which is assigned in advance and is included in a cache; causing the host to generate a writing completion signal for the first writing command; and causing the host to issue a second writing command.

Abstract: Provided is a method of writing data of a storage system. The method includes causing a host to issue a first writing command; causing the host, when a queue depth of the first writing command is a first value, to store the first writing command in an entry which is assigned in advance and is included in a cache; causing the host to generate a writing completion signal for the first writing command; and causing the host to issue a second writing command.